TRCRSCTLR<n> Trace Resource Selection Control Register <n> when FEAT_ETE is implemented, System register access to the trace unit registers is implemented, and (UInt(TRCIDR4.NUMRSPAIR) + 1) * 2 > n 2 31 TRCRSCTLR<n> Architectural External 31 0 31 0 31 0 31 0 Controls the selection of the resources in the trace unit. Trace Resource selector 0 always returns FALSE. Resource selector 1 always returns TRUE. Resource selectors are implemented in pairs. Each odd numbered resource selector is part of a pair with the even numbered resource selector that is numbered as one less than it. For example, resource selectors 2 and 3 form a pair. TRCRSCTLR<n> is a 64-bit register. 63 22 63:22 Reserved, RES0. PAIRINV 21 21 0 Controls whether the combined result from a resource selector pair is inverted. If: A is the register TRCRSCTLR<n>. B is the register TRCRSCTLR<n+1>. Then the combined output of the 2 resource selectors A and B depends on the value of (A.PAIRINV, A.INV, B.INV) as follows: 0b000 -> A and B. 0b001 -> Reserved. 0b010 -> not(A) and B. 0b011 -> not(A) and not(B). 0b100 -> not(A) or not(B). 0b101 -> not(A) or B. 0b110 -> Reserved. 0b111 -> A or B. 0b0 Do not invert the combined output of the 2 resource selectors. 0b1 Invert the combined output of the 2 resource selectors. AU When n is even 21 21 21 Reserved, RES0. Otherwise INV 20 20 20 Controls whether the resource, that TRCRSCTLR<n>.GROUP and TRCRSCTLR<n>.SELECT selects, is inverted. 0b0 Do not invert the output of this selector. 0b1 Invert the output of this selector. AU GROUP 19 16 19:16 Selects a group of resources. All other values are reserved. 0b0000 External Input Selectors. 0b0001 PE Comparator Inputs. 0b0010 Counters and Sequencer. 0b0011 Single-shot Comparator Controls. 0b0100 Single Address Comparators. 0b0101 Address Range Comparators. 0b0110 Context Identifier Comparators. 0b0111 Virtual Context Identifier Comparators. AU SELECT 15 0 15:0 Resource Specific Controls. Contains the controls specific to the resource group selected by GROUP, described in the following sections. External Input Selectors 15 4 15:4 Reserved, RES0. EXTIN[<m>] 3 0 3:0 Selects one or more External Inputs. This bit is RES0 if m >= TRCIDR5.NUMEXTINSEL. 3 0 0b0 Ignore EXTIN <m>. 0b1 Select EXTIN <m>. AU PE Comparator Inputs 15 8 15:8 Reserved, RES0. PECOMP[<m>] 7 0 7:0 Selects one or more PE Comparator Inputs. This bit is RES0 if m >= TRCIDR4.NUMPC. 7 0 0b0 Ignore PE Comparator Input <m>. 0b1 Select PE Comparator Input <m>. AU Counters and Sequencer 15 8 15:8 Reserved, RES0. SEQUENCER[<m>] 7 4 7:4 Sequencer states. This bit is RES0 if m >= TRCIDR5.NUMSEQSTATE. 3 0 0b0 Ignore Sequencer state <m>. 0b1 Select Sequencer state <m>. AU COUNTERS[<m>] 3 0 3:0 Counters resources at zero. This bit is RES0 if m >= TRCIDR5.NUMCNTR. 3 0 0b0 Ignore Counter <m>. 0b1 Select Counter <m> is zero. AU Single-shot Comparator Controls 15 8 15:8 Reserved, RES0. SINGLE_SHOT[<m>] 7 0 7:0 Selects one or more Single-shot Comparator Controls. This bit is RES0 if m >= TRCIDR4.NUMSSCC. 7 0 0b0 Ignore Single-shot Comparator Control <m>. 0b1 Select Single-shot Comparator Control <m>. AU Single Address Comparators SAC[<m>] 15 0 15:0 Selects one or more Single Address Comparators. This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS. 15 0 0b0 Ignore Single Address Comparator <m>. 0b1 Select Single Address Comparator <m>. AU Address Range Comparators 15 8 15:8 Reserved, RES0. ARC[<m>] 7 0 7:0 Selects one or more Address Range Comparators. This bit is RES0 if m >= TRCIDR4.NUMACPAIRS. 7 0 0b0 Ignore Address Range Comparator <m>. 0b1 Select Address Range Comparator <m>. AU Context Identifier Comparators 15 8 15:8 Reserved, RES0. CID[<m>] 7 0 7:0 Selects one or more Context Identifier Comparators. This bit is RES0 if m >= TRCIDR4.NUMCIDC. 7 0 0b0 Ignore Context Identifier Comparator <m>. 0b1 Select Context Identifier Comparator <m>. AU Virtual Context Identifier Comparators 15 8 15:8 Reserved, RES0. VMID[<m>] 7 0 7:0 Selects one or more Virtual Context Identifier Comparators. This bit is RES0 if m >= TRCIDR4.NUMVMIDC. 7 0 0b0 Ignore Virtual Context Identifier Comparator <m>. 0b1 Select Virtual Context Identifier Comparator <m>. AU Must be programmed if any of the following are true: TRCCNTCTLR<a>.RLDEVENT_TYPE == 0 and TRCCNTCTLR<a>.RLDEVENT_SEL == n. TRCCNTCTLR<a>.RLDEVENT_TYPE == 1 and TRCCNTCTLR<a>.RLDEVENT_SEL == n/2. TRCCNTCTLR<a>.CNTEVENT_TYPE == 0 and TRCCNTCTLR<a>.CNTEVENT_SEL == n. TRCCNTCTLR<a>.CNTEVENT_TYPE == 1 and TRCCNTCTLR<a>.CNTEVENT_SEL == n/2. TRCEVENTCTL0R.EVENT0_TYPE == 0 and TRCEVENTCTL0R.EVENT0_SEL == n. TRCEVENTCTL0R.EVENT0_TYPE == 1 and TRCEVENTCTL0R.EVENT0_SEL == n/2. TRCEVENTCTL0R.EVENT1_TYPE == 0 and TRCEVENTCTL0R.EVENT1_SEL == n. TRCEVENTCTL0R.EVENT1_TYPE == 1 and TRCEVENTCTL0R.EVENT1_SEL == n/2. TRCEVENTCTL0R.EVENT2_TYPE == 0 and TRCEVENTCTL0R.EVENT2_SEL == n. TRCEVENTCTL0R.EVENT2_TYPE == 1 and TRCEVENTCTL0R.EVENT2_SEL == n/2. TRCEVENTCTL0R.EVENT3_TYPE == 0 and TRCEVENTCTL0R.EVENT3_SEL == n. TRCEVENTCTL0R.EVENT3_TYPE == 1 and TRCEVENTCTL0R.EVENT3_SEL == n/2. TRCSEQEVR<a>.B_TYPE == 0 and TRCSEQEVR<a>.B_SEL = n. TRCSEQEVR<a>.B_TYPE == 1 and TRCSEQEVR<a>.B_SEL = n/2. TRCSEQEVR<a>.F_TYPE == 0 and TRCSEQEVR<a>.F_SEL = n. TRCSEQEVR<a>.F_TYPE == 1 and TRCSEQEVR<a>.F_SEL = n/2. TRCSEQRSTEVR.RST_TYPE == 0 and TRCSEQRSTEVR.RST_SEL == n. TRCSEQRSTEVR.RST_TYPE == 1 and TRCSEQRSTEVR.RST_SEL == n/2. TRCTSCTLR.EVENT_TYPE == 0 and TRCTSCTLR.EVENT_SEL == n. TRCTSCTLR.EVENT_TYPE == 1 and TRCTSCTLR.EVENT_SEL == n/2. TRCVICTLR.EVENT_TYPE == 0 and TRCVICTLR.EVENT_SEL == n. TRCVICTLR.EVENT_TYPE == 1 and TRCVICTLR.EVENT_SEL == n/2. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 2-31 MRS <Xt>, TRCRSCTLR<m> let m:integer = UInt(op2[0] :: CRm[3:0]); if m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCRSCTLR(m); end; end; 2-31 MSR TRCRSCTLR<m>, <Xt> let m:integer = UInt(op2[0] :: CRm[3:0]); if m >= NUM_TRACE_RESOURCE_SELECTOR_PAIRS * 2 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCRSCTLR(m) = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel