TRCSYNCPR
Trace Synchronization Period Register
when FEAT_ETE is implemented and System register access to the trace unit registers is implemented
TRCSYNCPR
Architectural
External
31
0
31
0
31
0
31
0
Controls how often trace protocol synchronization requests occur.
Trace
TRCSYNCPR is a 64-bit register.
63
5
63:5
Reserved, RES0.
PERIOD
4
0
4:0
Defines the number of bytes of trace between each periodic trace protocol synchronization request.
Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is CONSTRAINED UNPREDICTABLE and one of the following behaviors occurs:
No trace protocol synchronization requests are generated by this counter.
Trace protocol synchronization requests occur at the specified period.
Trace protocol synchronization requests occur at some other UNKNOWN period which can vary.
0b00000
Trace protocol synchronization is disabled.
0b01000
Trace protocol synchronization request occurs after 28 bytes of trace.
0b01001
Trace protocol synchronization request occurs after 29 bytes of trace.
0b01010
Trace protocol synchronization request occurs after 210 bytes of trace.
0b01011
Trace protocol synchronization request occurs after 211 bytes of trace.
0b01100
Trace protocol synchronization request occurs after 212 bytes of trace.
0b01101
Trace protocol synchronization request occurs after 213 bytes of trace.
0b01110
Trace protocol synchronization request occurs after 214 bytes of trace.
0b01111
Trace protocol synchronization request occurs after 215 bytes of trace.
0b10000
Trace protocol synchronization request occurs after 216 bytes of trace.
0b10001
Trace protocol synchronization request occurs after 217 bytes of trace.
0b10010
Trace protocol synchronization request occurs after 218 bytes of trace.
0b10011
Trace protocol synchronization request occurs after 219 bytes of trace.
0b10100
Trace protocol synchronization request occurs after 220 bytes of trace.
AU
Must be programmed if TRCIDR3.SYNCPR == 0.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
MRS <Xt>, TRCSYNCPR
if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then
Undefined();
elsif CPACR_EL1().TTA == '1' then
AArch64_SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2().TTA == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRCSYNCPR();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then
Undefined();
elsif CPTR_EL2().TTA == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRCSYNCPR();
end;
elsif PSTATE.EL == EL3 then
if CPTR_EL3().TTA == '1' then
AArch64_SystemAccessTrap(EL3, 0x18);
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRCSYNCPR();
end;
end;
MSR TRCSYNCPR, <Xt>
if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then
Undefined();
elsif CPACR_EL1().TTA == '1' then
AArch64_SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && CPTR_EL2().TTA == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
TRCSYNCPR() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then
Undefined();
elsif CPTR_EL2().TTA == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
TRCSYNCPR() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
if CPTR_EL3().TTA == '1' then
AArch64_SystemAccessTrap(EL3, 0x18);
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
TRCSYNCPR() = X{64}(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel