TRCVICTLR Trace ViewInst Main Control Register when FEAT_ETE is implemented and System register access to the trace unit registers is implemented TRCVICTLR Architectural External 31 0 31 0 31 0 31 0 Controls instruction trace filtering. Trace TRCVICTLR is a 64-bit register. 63 27 63:27 Reserved, RES0. EXLEVEL_RL_EL2 26 26 0 Filter instruction trace for EL2 in Realm state. 0b0 When TRCVICTLR.EXLEVEL_NS_EL2 is 0 the trace unit generates instruction trace for EL2 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL2 is 1 the trace unit does not generate instruction trace for EL2 in Realm state. 0b1 When TRCVICTLR.EXLEVEL_NS_EL2 is 0 the trace unit does not generate instruction trace for EL2 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL2 is 1 the trace unit generates instruction trace for EL2 in Realm state. AU When FEAT_RME is implemented 26 26 26 Reserved, RES0. Otherwise EXLEVEL_RL_EL1 25 25 0 Filter instruction trace for EL1 in Realm state. 0b0 When TRCVICTLR.EXLEVEL_NS_EL1 is 0 the trace unit generates instruction trace for EL1 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL1 is 1 the trace unit does not generate instruction trace for EL1 in Realm state. 0b1 When TRCVICTLR.EXLEVEL_NS_EL1 is 0 the trace unit does not generate instruction trace for EL1 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL1 is 1 the trace unit generates instruction trace for EL1 in Realm state. AU When FEAT_RME is implemented 25 25 25 Reserved, RES0. Otherwise EXLEVEL_RL_EL0 24 24 0 Filter instruction trace for EL0 in Realm state. 0b0 When TRCVICTLR.EXLEVEL_NS_EL0 is 0 the trace unit generates instruction trace for EL0 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL0 is 1 the trace unit does not generate instruction trace for EL0 in Realm state. 0b1 When TRCVICTLR.EXLEVEL_NS_EL0 is 0 the trace unit does not generate instruction trace for EL0 in Realm state. When TRCVICTLR.EXLEVEL_NS_EL0 is 1 the trace unit generates instruction trace for EL0 in Realm state. AU When FEAT_RME is implemented 24 24 24 Reserved, RES0. Otherwise 23 23 23 Reserved, RES0. EXLEVEL_NS_EL2 22 22 0 Filter instruction trace for EL2 in Non-secure state. 0b0 The trace unit generates instruction trace for EL2 in Non-secure state. 0b1 The trace unit does not generate instruction trace for EL2 in Non-secure state. AU When Non-secure EL2 is implemented 22 22 22 Reserved, RES0. Otherwise EXLEVEL_NS_EL1 21 21 0 Filter instruction trace for EL1 in Non-secure state. 0b0 The trace unit generates instruction trace for EL1 in Non-secure state. 0b1 The trace unit does not generate instruction trace for EL1 in Non-secure state. AU When Non-secure EL1 is implemented 21 21 21 Reserved, RES0. Otherwise EXLEVEL_NS_EL0 20 20 0 Filter instruction trace for EL0 in Non-secure state. 0b0 The trace unit generates instruction trace for EL0 in Non-secure state. 0b1 The trace unit does not generate instruction trace for EL0 in Non-secure state. AU When Non-secure EL0 is implemented 20 20 20 Reserved, RES0. Otherwise EXLEVEL_S_EL3 19 19 0 Filter instruction trace for EL3. 0b0 The trace unit generates instruction trace for EL3. 0b1 The trace unit does not generate instruction trace for EL3. AU When EL3 is implemented 19 19 19 Reserved, RES0. Otherwise EXLEVEL_S_EL2 18 18 0 Filter instruction trace for EL2 in Secure state. 0b0 The trace unit generates instruction trace for EL2 in Secure state. 0b1 The trace unit does not generate instruction trace for EL2 in Secure state. AU When Secure EL2 is implemented 18 18 18 Reserved, RES0. Otherwise EXLEVEL_S_EL1 17 17 0 Filter instruction trace for EL1 in Secure state. 0b0 The trace unit generates instruction trace for EL1 in Secure state. 0b1 The trace unit does not generate instruction trace for EL1 in Secure state. AU When Secure EL1 is implemented 17 17 17 Reserved, RES0. Otherwise EXLEVEL_S_EL0 16 16 0 Filter instruction trace for EL0 in Secure state. 0b0 The trace unit generates instruction trace for EL0 in Secure state. 0b1 The trace unit does not generate instruction trace for EL0 in Secure state. AU When Secure EL0 is implemented 16 16 16 Reserved, RES0. Otherwise 15 12 15:12 Reserved, RES0. TRCERR 11 11 0 Controls the forced tracing of System Error exceptions. 0b0 Forced tracing of System Error exceptions is disabled. 0b1 Forced tracing of System Error exceptions is enabled. AU When TRCIDR3.TRCERR == '1' 11 11 11 Reserved, RES0. Otherwise TRCRESET 10 10 10 Controls the forced tracing of PE Resets. 0b0 Forced tracing of PE Resets is disabled. 0b1 Forced tracing of PE Resets is enabled. AU SSSTATUS 9 9 9 ViewInst start/stop function status. Before software enables the trace unit, it must write to this field to set the initial state of the ViewInst start/stop function. If the ViewInst start/stop function is not used then set this field to 1. Arm recommends that the value of this field is set before each trace session begins. If the trace unit becomes disabled while a start point or stop point is still speculative, then the value of TRCVICTLR.SSSTATUS is UNKNOWN and might represent the result of a speculative start point or stop point. If software which is running on the PE being traced disables the trace unit, either by clearing TRCPRGCTLR.EN or locking the OS Lock, Arm recommends that a DSB and an ISB instruction are executed before disabling the trace unit to prevent any start points or stop points being speculative at the point of disabling the trace unit. This procedure assumes that all start points or stop points occur before the barrier instructions are executed. The procedure does not guarantee that there are no speculative start points or stop points when disabling, although it helps minimize the probability. 0b0 Stopped State. The ViewInst start/stop function is in the stopped state. 0b1 Started State. The ViewInst start/stop function is in the started state. AU TRCIDR4.NUMACPAIRS == '0000' TRCIDR4.NUMPC == '0000' RES1 RW 8 8 8 Reserved, RES0. EVENT_TYPE 7 7 0 Chooses the type of Resource Selector. 0b0 A single Resource Selector. TRCVICTLR.EVENT.SEL[4:0] selects the single Resource Selector, from 0-31, used to activate the resource event. 0b1 A Boolean-combined pair of Resource Selectors. TRCVICTLR.EVENT.SEL[3:0] selects the Resource Selector pair, from 0-15, that has a Boolean function that is applied to it whose output is used to activate the resource event. TRCVICTLR.EVENT.SEL[4] is RES0. AU When TRCIDR4.NUMRSPAIR != '0000' 7 7 7 Reserved, RES0. Otherwise 6 5 6:5 Reserved, RES0. EVENT_SEL 4 0 4:0 Defines the selected Resource Selector or pair of Resource Selectors. TRCVICTLR.EVENT.TYPE controls whether TRCVICTLR.EVENT.SEL is the index of a single Resource Selector, or the index of a pair of Resource Selectors. If an unimplemented Resource Selector is selected using this field, the behavior of the resource event is UNPREDICTABLE, and the resource event might fire or might not fire when the resources are not in the Paused state. If an unimplemented Resource Selector is selected using this field, the value returned on a direct read of this field is UNKNOWN. Selecting Resource Selector pair 0 using this field is UNPREDICTABLE, and the resource event might fire or might not fire when the resources are not in the Paused state. AU When TRCIDR4.NUMRSPAIR != '0000' Reserved 4 0 4:0 This field is reserved: Bits [4:1] are RES0. Bit [0] is RES1. When TRCIDR4.NUMRSPAIR == '0000' 4 0 4:0 Reserved, RES0. Otherwise Must be programmed. Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states. MRS <Xt>, TRCVICTLR if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRCVICTLR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVICTLR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVICTLR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCVICTLR(); end; end; MSR TRCVICTLR, <Xt> if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRCVICTLR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVICTLR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVICTLR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCVICTLR() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel