TRFCR_EL1 Trace Filter Control Register (EL1) when FEAT_TRF is implemented and FEAT_AA64 is implemented TRFCR Architectural AArch32 31 0 31 0 31 0 31 0 Provides EL1 controls for Trace. Debug TRFCR_EL1 is a 64-bit register. 63 12 63:12 Reserved, RES0. DnVM 11 11 0 Reserved for software use in nested virtualization. See also TRFCR_EL2.DnVM. AU When FEAT_TRBEv1p1 is implemented and FEAT_NV is implemented 11 11 11 Reserved, RES0. Otherwise KE 10 10 0 Kernel exception enable for TRBE Profiling exceptions taken to EL1. 0b0 TRBE Profiling exceptions taken to EL1 are always masked at EL1. 0b1 Enabled TRBE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0. AU When FEAT_TRBE_EXC is implemented 10 10 10 Reserved, RES0. Otherwise EE 9 8 1:0 Exception Enable. For more information on the values reserved for software use in nested virtualization, see TRFCR_EL2.EE. If the Effective value of TRFCR_EL2.EE is 0b00, then the Effective value of TRFCR_EL1.EE is 0b00. 0b00 Disabled. TRBE Profiling exceptions for EL1 are disabled. All of the following apply: Unless enabled by a higher Exception level, TRBE Profiling exceptions are not generated. TRBSR_EL1.IRQ drives the interrupt request signal TRBIRQ. Accesses to TRBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1. 0b01 Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the TRBE Profiling exception and interrupt request signal TRBIRQ, and as 0b11 for the purpose of accesses to TRBSR_EL1. When FEAT_NV is implemented 0b10 Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the TRBE Profiling exception and interrupt request signal TRBIRQ, and accesses to TRBSR_EL1. When FEAT_NV is implemented 0b11 Enabled. TRBE Profiling exceptions for EL1 are enabled, as follows: All trace buffer management events are recorded in TRBSR_EL1, unless they are configured to be recorded in TRBSR_EL3 by MDCR_EL3.TRBEE or TRBSR_EL2 by TRFCR_EL2.EE. TRBE Profiling exceptions are generated and taken to EL1 when unmasked and TRBSR_EL1.IRQ is 1, unless the Effective value of HCR_EL2.TGE is 1, in which case the exception is taken to EL2. The interrupt request signal TRBIRQ is not asserted. '00' AU When FEAT_TRBE_EXC is implemented 9 8 9:8 Reserved, RES0. Otherwise 7 7 7 Reserved, RES0. TS 6 5 6:5 Timestamp Control. Controls which timebase is used for trace timestamps. All other values are reserved. If any of the following are true, then this field is ignored by the PE: EL2 is implemented and TRFCR_EL2.TS is not 0b00. SelfHostedTraceEnabled() == FALSE. 0b00 Reserved for software use in nested virtualization. Behaves as 0b01. See also TRFCR_EL2.TS, When FEAT_NV2p1 is implemented 0b01 Virtual timestamp. The traced timestamp is the physical counter value minus the value of CNTVOFF_EL2. 0b10 Guest physical timestamp. The traced timestamp is the physical counter value minus a physical offset. If any of the following are true, then the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2: SCR_EL3.ECVEn == 0. CNTHCTL_EL2.ECV == 0. FEAT_ECV_POFF is not implemented. When FEAT_ECV is implemented 0b11 Physical timestamp. The traced timestamp is the physical counter value. AU 4 4 4 Reserved, RES0. CX 3 3 0 Reserved for software use in nested virtualization. See also TRFCR_EL2.CX. AU When FEAT_NV2p1 is implemented 3 3 3 Reserved, RES0. Otherwise 2 2 2 Reserved, RES0. E1TRE 1 1 1 EL1 Trace Enable. If any of the following are true, then this field is ignored by the PE: SelfHostedTraceEnabled() == FALSE. The Effective value of HCR_EL2.TGE is 1. 0b0 Trace is prohibited at EL1. 0b1 Trace is allowed at EL1. '0' E0TRE 0 0 0 EL0 Trace Enable. If any of the following are true, then this field is ignored by the PE: SelfHostedTraceEnabled() == FALSE. The Effective value of HCR_EL2.TGE is 1. 0b0 Trace is prohibited at EL0. 0b1 Trace is allowed at EL0. '0' MRS <Xt>, TRFCR_EL1 if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif EL2Enabled() && MDCR_EL2().TTRF == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x880); else X{64}(t) = TRFCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TRFCR_EL2(); else X{64}(t) = TRFCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TRFCR_EL1(); end; MSR TRFCR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRFCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TTRF == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x880) = X{64}(t); else TRFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then TRFCR_EL2() = X{64}(t); else TRFCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TRFCR_EL1() = X{64}(t); end; MRS <Xt>, TRFCR_EL12 When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x880); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TRFCR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TRFCR_EL1(); else Undefined(); end; end; MSR TRFCR_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_TRF) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x880) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TTRF == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TTRF == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TRFCR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TRFCR_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel