TTBR0_EL3
Translation Table Base Register 0 (EL3)
when EL3 is implemented and FEAT_AA64 is implemented
Holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL3 translation regime, and other information for this translation regime.
Memory
TTBR0_EL3 is a 64-bit register.
When FEAT_D128 is implemented and TCR_EL3.D128 == '1'
63
56
63:56
Reserved, RES0.
BADDR
55
5
55:5
Bits A[55:x] of the stage 1 translation table base address bits are in register bits[55:x].
Bits A[(x-1):0] of the stage 1 translation table base address are zero.
Address bit x is the minimum address bit required to align the translation table to the size of the table. x is calculated based on LOG2(StartTableSize), as described in VMSAv9-128. The smallest permitted value of x is 5.
AU
4
3
4:3
Reserved, RES0.
SKL
2
1
2:1
Skip Level associated with translation table walks using TTBR0_EL3.
This determines the number of levels to be skipped from the regular start level of the stage 1 EL3 translation table walks using TTBR0_EL3.
0b00
Skip 0 level from the regular start level.
0b01
Skip 1 level from the regular start level.
0b10
Skip 2 levels from the regular start level.
0b11
Skip 3 levels from the regular start level.
AU
CnP
0
0
0
Common not Private. This bit indicates whether each entry that is pointed to by TTBR0_EL3 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1.
This bit is permitted to be cached in a TLB.
If the value of the TTBR0_EL3.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL3s do not point to the same translation table entries the results of translations using TTBR0_EL3 are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.
0b0
The translation table entries pointed to by TTBR0_EL3, for the current translation regime, are permitted to differ from corresponding entries for TTBR0_EL3 for other PEs in the Inner Shareable domain. This is not affected by the value of TTBR0_EL3.CnP on those other PEs.
0b1
The translation table entries pointed to by TTBR0_EL3 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1 and the translation table entries are pointed to by TTBR0_EL3.
AU
When FEAT_D128 is not implemented or TCR_EL3.D128 == '0'
63
48
63:48
Reserved, RES0.
BADDR
47
1
47:1
Bits A[47:x] of the stage 1 translation table base address bits are in register bits[47:x].
Bits A[(x-1):0] of the stage 1 translation table base address are zero.
Address bit x is the minimum address bit required to align the translation table to the size of the table. The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL3.T0SZ, the translation stage, and the translation granule size.
The BADDR field represents a 52-bit address if any of the following apply:
The value of TCR_EL3.PS represents an OA size of 52 bits.
The Effective value of TCR_EL3.DS is 1.
When TTBR0_EL3.BADDR represents a 52-bit addresses, all of the following apply:
Bits A[51:48] of the stage 1 translation table base address bits are in register bits[5:2].
Register bit[1] is RES0.
The smallest permitted value of x is 6.
When x>6, register bits[(x-1):6] are RES0.
Otherwise, all of the following apply:
Register bits[(x-1):1] are RES0.
If 52-bit PA is supported, then bits A[51:48] of the stage 1 translation table base address are treated as 0b0000.
If BADDR represents a 52-bit address, and the translation table has fewer than eight entries, the table must be aligned to 64 bytes. Otherwise the translation table must be aligned to the size of the table.For the 64KB granule, if 52-bit PA is not supported, and the value of TCR_EL3.PS is 0b110 or 0b111, one of the following IMPLEMENTATION DEFINED behaviors occur:BADDR uses the extended format to represent a 52-bit base address.BADDR does not use the extended format.
When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation supports a 56 bit PA size, bits A[55:52] of the stage 1 translation table base address are zero.If any register bit[47:1] that is defined as RES0 has the value 1 when a translation table walk is done using TTBR0_EL3, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
Bits A[(x-1):0] of the stage 1 translation table base address are treated as if all the bits are zero. The value read back from the corresponding register bits is either the value written to the register or zero.
The result of the calculation of an address for a translation table walk using this register can be corrupted in those bits that are nonzero.
AU
CnP
0
0
0
Common not Private. This bit indicates whether each entry that is pointed to by TTBR0_EL3 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1.
This bit is permitted to be cached in a TLB.
If the value of the TTBR0_EL3.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL3s do not point to the same translation table entries the results of translations using TTBR0_EL3 are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.
0b0
The translation table entries pointed to by TTBR0_EL3, for the current translation regime, are permitted to differ from corresponding entries for TTBR0_EL3 for other PEs in the Inner Shareable domain. This is not affected by the value of TTBR0_EL3.CnP on those other PEs.
0b1
The translation table entries pointed to by TTBR0_EL3 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1 and the translation table entries are pointed to by TTBR0_EL3.
AU
When FEAT_TTCNP is implemented
0
0
0
Reserved, RES0.
Otherwise
When FEAT_D128 is implemented and TCR_EL3.D128 == '1'
When FEAT_D128 is not implemented or TCR_EL3.D128 == '0'
MRS <Xt>, TTBR0_EL3
if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
X{64}(t) = TTBR0_EL3();
end;
MSR TTBR0_EL3, <Xt>
if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().TTBR0_EL3 == '1' then
AArch64_SystemAccessTrap(EL3, 0x18);
else
TTBR0_EL3() = X{64}(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel