VDISR_EL3 Virtual Deferred Interrupt Status Register (EL3) when FEAT_E3DSE is implemented Records that a delegated SError exception has been consumed by an ESB instruction executed at EL2, EL1, or EL0 when the Effective value of SCR_EL3.DSE is 1. An indirect write to VDISR_EL3 made by an ESB instruction does not require an explicit synchronization operation for the value written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction. RAS The encoding for this register is subject to change. VDISR_EL3 is a 64-bit register. 63 32 63:32 Reserved, RES0. A 31 31 31 Set to 1 when an ESB instruction defers a delegated SError exception. AU 30 25 30:25 Reserved, RES0. IDS 24 24 24 The value copied from VSESR_EL3.IDS. AU ISS 23 0 23:0 The value copied from VSESR_EL3.ISS. AU An indirect write to VDISR_EL3 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction. The accessibility pseudocode for DISR_EL1 has not been updated to show the effect of VDISR_EL3. MRS <Xt>, VDISR_EL3 if !IsFeatureImplemented(FEAT_E3DSE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = VDISR_EL3(); end; MSR VDISR_EL3, <Xt> if !IsFeatureImplemented(FEAT_E3DSE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then VDISR_EL3() = X{64}(t); end; MRS <Xt>, DISR_EL1 if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then X{64}(t) = VDISR_EL2(); elsif HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then X{64}(t) = VDISR_EL3(); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then X{64}(t) = Zeros{64}; else X{64}(t) = DISR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then X{64}(t) = VDISR_EL3(); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then X{64}(t) = Zeros{64}; else X{64}(t) = DISR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = DISR_EL1(); end; MSR DISR_EL1, <Xt> if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then VDISR_EL2() = X{64}(t); elsif HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then VDISR_EL3() = X{64}(t); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then return; else DISR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then VDISR_EL3() = X{64}(t); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then return; else DISR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then DISR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel