VMPIDR_EL2 Virtualization Multiprocessor ID Register when FEAT_AA64 is implemented VMPIDR Architectural AArch32 31 0 31 0 31 0 31 0 Holds the value of the Virtualization Multiprocessor ID. This is the value returned by EL1 reads of MPIDR_EL1, which in a multiprocessor system, provides an additional PE identification system. Virt If EL2 is not implemented, reads of this register return the value of the MPIDR_EL1 and writes to the register are ignored. This register has no effect if EL2 is not enabled in the current Security state. VMPIDR_EL2 is a 64-bit register. 63 40 63:40 Reserved, RES0. Aff3 39 32 39:32 Affinity level 3. See the description of VMPIDR_EL2.Aff0 for more information. Aff3 is not supported in AArch32 state. AU 31 31 31 Reserved, RES1. U 30 30 30 Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. 0b0 Processor is part of a multiprocessor system. 0b1 Processor is part of a uniprocessor system. AU 29 25 29:25 Reserved, RES0. MT 24 24 24 Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of VMPIDR_EL2.Aff0 for more information about affinity levels. 0b0 Performance of PEs at the lowest affinity level is largely independent. 0b1 Performance of PEs at the lowest affinity level is very interdependent. AU Aff2 23 16 23:16 Affinity level 2. See the description of VMPIDR_EL2.Aff0 for more information. AU Aff1 15 8 15:8 Affinity level 1. See the description of VMPIDR_EL2.Aff0 for more information. AU Aff0 7 0 7:0 Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole. AU MRS <Xt>, VMPIDR_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x050); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = VMPIDR_EL2(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then X{64}(t) = MPIDR_EL1(); else X{64}(t) = VMPIDR_EL2(); end; end; MSR VMPIDR_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x050) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then VMPIDR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return; else VMPIDR_EL2() = X{64}(t); end; end; MRS <Xt>, MPIDR_EL1 if !IsFeatureImplemented(FEAT_AA64) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().MPIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then X{64}(t) = VMPIDR_EL2(); else X{64}(t) = MPIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = MPIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = MPIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel