<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>VNCR_EL2</reg_short_name>
        
        <reg_long_name>Virtual Nested Control Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_NV2 is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>When <xref linkend="#FEAT_NV2">FEAT_NV2</xref> is implemented, holds the base address that is used to define the memory location that is accessed by transformed reads and writes of System registers.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Generic System Control</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>This register has no effect if EL2 is not enabled in the current Security state.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>VNCR_EL2 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_12" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>BADDR</field_name>
    <field_msb>63</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>63:12</rel_range>
    <field_description order="before"><para>Base Address. When a register read/write is transformed to be a Load or Store, the address of the load/store is to VNCR_EL2.BADDR:Offset&lt;11:0&gt;.</para>
<para>Bits[63:n] are RESS where n is one of the following:</para>
<list type="unordered">
<listitem><content>If <xref linkend="#FEAT_LVA3">FEAT_LVA3</xref> is implemented, n is 57.</content>
</listitem><listitem><content>Otherwise, if <xref linkend="#FEAT_LVA">FEAT_LVA</xref> is implemented, n is 53.</content>
</listitem><listitem><content>If FEAT_LVA is not implemented, n is 49.</content>
</listitem></list>
<para>If the bits marked as RESS do not all have the same value as bit[n-1], then there is a <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> choice between:</para>
<list type="unordered">
<listitem><content>Generating a Translation fault when translating the transformed register read/write.</content>
</listitem><listitem><content>The bits behave as the same value as bit[n-1] for all purposes other than reading back the register.</content>
</listitem><listitem><content>The bits are treated as the same value as bit[n-1] for all purposes.</content>
</listitem></list></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-11_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>11</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>11:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_12" msb="63" lsb="12"/>
  <fieldat id="fieldset_0-11_0" msb="11" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS VNCR_EL2" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, VNCR_EL2</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b100"/>
                
                <enc n="CRn" v="0b0010"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_NV2) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'1x1'} then
        X{64}(t) = NVMem(0x0B0);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    X{64}(t) = VNCR_EL2();
elsif PSTATE.EL == EL3 then
    X{64}(t) = VNCR_EL2();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister VNCR_EL2" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR VNCR_EL2, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b100"/>
                
                <enc n="CRn" v="0b0010"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b000"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_NV2) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if EffectiveHCR_EL2_NVx() IN {'1x1'} then
        NVMem(0x0B0) = X{64}(t);
    elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
        AArch64_SystemAccessTrap(EL2, 0x18);
    else
        Undefined();
    end;
elsif PSTATE.EL == EL2 then
    VNCR_EL2() = X{64}(t);
elsif PSTATE.EL == EL3 then
    VNCR_EL2() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>