VSESR_EL2 Virtual SError Exception Syndrome Register (EL2) when FEAT_RAS is implemented VDFSR Architectural AArch32 31 0 31 0 31 0 31 0 Provides the syndrome value reported to software on taking a virtual SError exception to EL1, or on executing an ESB instruction at EL1. When the virtual SError exception injected using HCR_EL2.VSE is taken to EL1 using AArch64, then the syndrome value is reported in ESR_EL1. When the virtual SError exception injected using HCR_EL2.VSE is taken to EL1 using AArch32, then the syndrome value is reported in DFSR.{AET, ExT} and the remainder of DFSR is set as defined by VMSAv8-32. For more information, see The AArch32 Virtual Memory System Architecture. When the virtual SError exception injected using HCR_EL2.VSE is deferred by an ESB instruction, then the syndrome value is written to VDISR_EL2. RAS If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. VSESR_EL2 is a 64-bit register. When EL1 is using AArch32 63 16 63:16 Reserved, RES0. AET 15 14 15:14 When a virtual SError exception is taken to EL1 using AArch32, DFSR[15:14] is set to VSESR_EL2.AET. When a virtual SError exception is deferred by an ESB instruction, VDISR_EL2[15:14] is set to VSESR_EL2.AET. AU 13 13 13 Reserved, RES0. ExT 12 12 12 When a virtual SError exception is taken to EL1 using AArch32, DFSR[12] is set to VSESR_EL2.ExT. When a virtual SError exception is deferred by an ESB instruction, VDISR_EL2[12] is set to VSESR_EL2.ExT. AU 11 0 11:0 Reserved, RES0. When EL1 is using AArch64 63 25 63:25 Reserved, RES0. IDS 24 24 24 When a virtual SError exception is taken to EL1 using AArch64, ESR_EL1[24] is set to VSESR_EL2.IDS. When a virtual SError exception is deferred by an ESB instruction, VDISR_EL2[24] is set to VSESR_EL2.IDS. AU ISS 23 0 23:0 When a virtual SError exception is taken to EL1 using AArch64, ESR_EL1[23:0] is set to VSESR_EL2.ISS. When a virtual SError exception is deferred by an ESB instruction, VDISR_EL2[23:0] is set to VSESR_EL2.ISS. AU When EL1 is using AArch32 When EL1 is using AArch64 MRS <Xt>, VSESR_EL2 if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x508); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = VSESR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = VSESR_EL2(); end; MSR VSESR_EL2, <Xt> if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x508) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then VSESR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then VSESR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel