<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>VSESR_EL3</reg_short_name>
        
        <reg_long_name>Virtual SError Exception Syndrome Register (EL3)</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_E3DSE is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides the syndrome value reported to software when the Effective value of <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is 1 on taking a delegated SError exception to EL2 or EL1, or on executing an <instruction>ESB</instruction> instruction at EL2 or EL1.</para>

      </purpose_text>
      <purpose_text>
        <para>When the delegated SError exception injected using <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is taken to EL2 using AArch64, then the syndrome value is reported in <register_link state="AArch64" id="AArch64-esr_el2.xml">ESR_EL2</register_link>.</para>

      </purpose_text>
      <purpose_text>
        <para>When the delegated SError exception injected using <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is taken to EL1 using AArch64, then the syndrome value is reported in <register_link state="AArch64" id="AArch64-esr_el1.xml">ESR_EL1</register_link>.</para>

      </purpose_text>
      <purpose_text>
        <para>When the delegated SError exception injected using <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is deferred by an <instruction>ESB</instruction> instruction, then the syndrome value is written to <register_link state="AArch64" id="AArch64-vdisr_el3.xml">VDISR_EL3</register_link>.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>RAS</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>VSESR_EL3 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_25" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>25</field_lsb>
    <rel_range>63:25</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-24_24" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>IDS</field_name>
    <field_msb>24</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>24</rel_range>
    <field_description order="before"><para>When a delegated SError exception triggered by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is taken to EL2 or EL1 using AArch64, <xref linkend="#ESR_ELx">ESR_ELx</xref>[24] is set to VSESR_EL3.IDS.</para>
<para>When a delegated SError exception triggered by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is deferred by an <instruction>ESB</instruction> instruction, <register_link state="AArch64" id="AArch64-vdisr_el3.xml">VDISR_EL3</register_link>[24] is set to VSESR_EL3.IDS.</para></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-23_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ISS</field_name>
    <field_msb>23</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>23:0</rel_range>
    <field_description order="before"><para>When a delegated SError exception triggered by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is taken to EL2 or EL1 using AArch64, <xref linkend="#ESR_ELx">ESR_ELx</xref>[23:0] is set to VSESR_EL3.ISS.</para>
<para>When a delegated SError exception triggered by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.DSE is deferred by an <instruction>ESB</instruction> instruction, <register_link state="AArch64" id="AArch64-vdisr_el3.xml">VDISR_EL3</register_link>[23:0] is set to VSESR_EL3.ISS.</para></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_25" msb="63" lsb="25"/>
  <fieldat id="fieldset_0-24_24" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-23_0" msb="23" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS VSESR_EL3" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, VSESR_EL3</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b110"/>
                
                <enc n="CRn" v="0b0101"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b011"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_E3DSE) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    Undefined();
elsif PSTATE.EL == EL2 then
    Undefined();
elsif PSTATE.EL == EL3 then
    X{64}(t) = VSESR_EL3();
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister VSESR_EL3" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR VSESR_EL3, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b110"/>
                
                <enc n="CRn" v="0b0101"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b011"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_E3DSE) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    Undefined();
elsif PSTATE.EL == EL2 then
    Undefined();
elsif PSTATE.EL == EL3 then
    VSESR_EL3() = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>