AMCFGR Activity Monitors Configuration Register It is IMPLEMENTATION DEFINED whether AMCFGR is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented AMU 0xE00 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMU 0xE00 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMCFGR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_AMU_EXT32 is implemented AMCFGR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 when FEAT_AMU_EXT64 is implemented AMCFGR Architectural AArch32 31 0 31 0 31 0 31 0 Global configuration register for the activity monitors. Provides information on supported features, the number of counter groups implemented, the total number of activity monitor event counters implemented, and the size of the counters. AMCFGR is applicable to both the architected and the auxiliary counter groups. AMU AMCFGR is a: 64-bit register when FEAT_AMU_EXT64 is implemented 32-bit register otherwise When FEAT_AMU_EXT64 is implemented 63 32 63:32 Reserved, RES0. NCG 31 28 31:28 Defines the number of counter groups implemented, minus one. All other values are reserved. 0b0000 One counter group implemented. 0b0001 Two counter groups implemented. RO 27 25 27:25 Reserved, RES0. HDBG 24 24 24 Halt-on-debug supported. This feature must be supported, and so this bit is 1. 0b0 AMCR.HDBG is RES0. 0b1 AMCR.HDBG is read/write. RO 23 14 23:14 Reserved, RAZ. SIZE 13 8 13:8 Defines the size of the activity monitor event counters, minus one. The counters are 64-bit, so the value of this field is 0b111111. This field is used by software to determine the spacing of the counters in the memory-map. The counters are at doubleword-aligned addresses. Reads as 0b111111. RO N 7 0 7:0 Defines the number of activity monitor event counters implemented in all groups. One less than the sum of AMCFGR.CG1NC and AMCFGR.CG0NC. This field has an IMPLEMENTATION DEFINED value. RO NCG 31 28 31:28 Defines the number of counter groups implemented, minus one. All other values are reserved. 0b0000 One counter group implemented. 0b0001 Two counter groups implemented. RO 27 25 27:25 Reserved, RES0. HDBG 24 24 24 Halt-on-debug supported. This feature must be supported, and so this bit is 1. 0b0 AMCR.HDBG is RES0. 0b1 AMCR.HDBG is read/write. RO 23 14 23:14 Reserved, RAZ. SIZE 13 8 13:8 Defines the size of the activity monitor event counters, minus one. The counters are 64-bit, so the value of this field is 0b111111. This field is used by software to determine the spacing of the counters in the memory-map. The counters are at doubleword-aligned addresses. Reads as 0b111111. RO N 7 0 7:0 Defines the number of activity monitor event counters implemented in all groups. One less than the sum of AMCFGR.CG1NC and AMCFGR.CG0NC. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_AMU_EXT64 is implemented Accessible at offset 0xE00 from AMU When FEAT_AMU_EXT64 is implemented Accessible at offset 0xE00 from AMU When FEAT_AMU_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel