AMCGCR Activity Monitors Counter Group Configuration Register It is IMPLEMENTATION DEFINED whether AMCGCR is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented AMU 0xCE0 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMU 0xCE0 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMCGCR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_AMU_EXT32 is implemented AMCGCR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 when FEAT_AMU_EXT64 is implemented AMCGCR Architectural AArch32 31 0 31 0 31 0 31 0 Provides information on the number of activity monitor event counters implemented within each counter group. AMU AMCGCR is a: 64-bit register when FEAT_AMU_EXT64 is implemented 32-bit register otherwise When FEAT_AMU_EXT64 is implemented 63 16 63:16 Reserved, RES0. CG1NC 15 8 15:8 Counter Group 1 Number of Counters. Highest index of the implemented counters in the auxiliary counter group, plus one. Zero indicates that there are no counters in the auxiliary counter group. In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16. If FEAT_AMUv1p1 is implemented, then AMCG1IDR_EL0 further defines which auxiliary counters are implemented, and the counters in the auxiliary counter group might be implemented non-contiguously. This field has an IMPLEMENTATION DEFINED value. RO CG0NC 7 0 7:0 Counter Group 0 Number of Counters. The number of counters in the architected counter group. Reads as 0x04. RO 31 16 31:16 Reserved, RES0. CG1NC 15 8 15:8 Counter Group 1 Number of Counters. Highest index of the implemented counters in the auxiliary counter group, plus one. Zero indicates that there are no counters in the auxiliary counter group. In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16. If FEAT_AMUv1p1 is implemented, then AMCG1IDR_EL0 further defines which auxiliary counters are implemented, and the counters in the auxiliary counter group might be implemented non-contiguously. This field has an IMPLEMENTATION DEFINED value. RO CG0NC 7 0 7:0 Counter Group 0 Number of Counters. The number of counters in the architected counter group. Reads as 0x04. RO When FEAT_AMU_EXT64 is implemented Accessible at offset 0xCE0 from AMU When FEAT_AMU_EXT64 is implemented Accessible at offset 0xCE0 from AMU When FEAT_AMU_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel