AMCNTEN Activity Monitors Count Set and Clear Register It is IMPLEMENTATION DEFINED whether AMCNTEN is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT64 is implemented AMU 0xC10 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO Control bits for the architected and auxiliary activity monitors event counters, AMEVCNTR0<n>. and AMEVCNTR1<n>. AMU AMCNTEN is a 64-bit register. 63 48 63:48 Reserved, RES0. P1<n> 47 32 47:32 Activity monitor event counter control bit for AMEVCNTR1<n>. Possible values of each bit are: 15 0 0b0 When read, means that AMEVCNTR1<n> is disabled. 0b1 When read, means that AMEVCNTR1<n> is enabled. 0x00000000 When n >= UInt(AMU.AMCGCR.CG1NC) RAZ/WI W1C 31 16 31:16 Reserved, RES0. 15 4 15:4 Reserved, RAZ/WI. This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture. P0<n> 3 0 3:0 Activity monitor event counter control bit for AMEVCNTR0<n>. AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.Possible values of each bit are: 3 0 0b0 When read, means that AMEVCNTR0<n> is disabled. 0b1 When read, means that AMEVCNTR0<n> is enabled. 0x00000000 When n >= 4 RAZ/WI W1C If there are no auxiliary monitor event counters implemented, reads of AMCNTEN[63:32] are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'. There are no implemented auxiliary activity monitor event counters when AMCFGR.NCG == 0b0000. Accessible at offset 0xC10 from AMU 2026-03-26 20:27:25 2026-03_rel