AMCNTENCLR1 Activity Monitors Count Enable Clear Register 1 It is IMPLEMENTATION DEFINED whether AMCNTENCLR1 is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented AMU 0xC24 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMCNTENCLR1_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 AMCNTENSET1_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 AMCNTENCLR1 Architectural AArch32 31 0 31 0 31 0 31 0 AMCNTENSET1 Architectural AArch32 31 0 31 0 31 0 31 0 AMCNTENSET1 Architectural External 31 0 31 0 31 0 31 0 Disable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>. AMU AMCNTENCLR1 is a 32-bit register. 31 16 31:16 Reserved, RES0. P<n> 15 0 15:0 Activity monitor event counter disable bit for AMEVCNTR1<n>. Possible values of each bit are: 15 0 0b0 When read, means that AMEVCNTR1<n> is disabled. 0b1 When read, means that AMEVCNTR1<n> is enabled. 0x00000000 When n >= UInt(AMU.AMCGCR.CG1NC) RAZ/WI When !IsG1ActivityMonitorImplemented(n) RAZ/WI W1C If there are no auxiliary monitor event counters implemented, reads of AMCNTENCLR1 are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'. There are no implemented auxiliary activity monitor event counters when AMCFGR.NCG == 0b0000. Accessible at offset 0xC24 from AMU When FEAT_AMU_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel