AMCNTENSET0 Activity Monitors Count Enable Set Register 0 It is IMPLEMENTATION DEFINED whether AMCNTENSET0 is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT32 is implemented AMU 0xC00 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMCNTENCLR0 Architectural External 31 0 31 0 31 0 31 0 AMCNTENCLR0_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 AMCNTENSET0_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 AMCNTENCLR0 Architectural AArch32 31 0 31 0 31 0 31 0 AMCNTENSET0 Architectural AArch32 31 0 31 0 31 0 31 0 Enable control bits for the architected activity monitors event counters, AMEVCNTR0<n>. AMU AMCNTENSET0 is a 32-bit register. 31 16 31:16 Reserved, RES0. 15 4 15:4 Reserved, RAZ/WI. This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture. P<n> 3 0 3:0 Activity monitor event counter enable bit for AMEVCNTR0<n>. AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.Possible values of each bit are: 3 0 0b0 When read, means that AMEVCNTR0<n> is disabled. 0b1 When read, means that AMEVCNTR0<n> is enabled. 0x00000000 When n >= 4 RAZ/WI W1S Accessible at offset 0xC00 from AMU 2026-03-26 20:27:25 2026-03_rel