AMCR Activity Monitors Control Register It is IMPLEMENTATION DEFINED whether AMCR is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented AMU 0xE04 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMU 0xE10 When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMCR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when FEAT_AMU_EXT32 is implemented AMCR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 when FEAT_AMU_EXT64 is implemented AMCR Architectural AArch32 31 0 31 0 31 0 31 0 Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups. AMU AMCR is a: 64-bit register when FEAT_AMU_EXT64 is implemented 32-bit register otherwise When FEAT_AMU_EXT64 is implemented 63 18 63:18 Reserved, RES0. CG1RZ 17 17 0 Counter Group 1 Read Zero. Reads from the memory-mapped view of AMEVCNTR1<n> are unaffected by this field. 0b0 System register reads of AMEVCNTR1<n> return the event count at all implemented and enabled Exception levels. 0b1 If the current Exception level is the highest implemented Exception level, System register reads of AMEVCNTR1<n> return the event count. Otherwise, reads of AMEVCNTR1<n> return a zero value. AU When FEAT_AMUv1p1 is implemented 17 17 17 Reserved, RES0. Otherwise 16 11 16:11 Reserved, RES0. HDBG 10 10 10 This bit controls whether activity monitor counting is halted when the PE is halted in Debug state. 0b0 Activity monitors do not halt counting when the PE is halted in Debug state. 0b1 Activity monitors halt counting when the PE is halted in Debug state. AU 9 0 9:0 Reserved, RES0. 31 18 31:18 Reserved, RES0. CG1RZ 17 17 0 Counter Group 1 Read Zero. Reads from the memory-mapped view of AMEVCNTR1<n> are unaffected by this field. 0b0 System register reads of AMEVCNTR1<n> return the event count at all implemented and enabled Exception levels. 0b1 If the current Exception level is the highest implemented Exception level, System register reads of AMEVCNTR1<n> return the event count. Otherwise, reads of AMEVCNTR1<n> return a zero value. AU When FEAT_AMUv1p1 is implemented 17 17 17 Reserved, RES0. Otherwise 16 11 16:11 Reserved, RES0. HDBG 10 10 10 This bit controls whether activity monitor counting is halted when the PE is halted in Debug state. 0b0 Activity monitors do not halt counting when the PE is halted in Debug state. 0b1 Activity monitors halt counting when the PE is halted in Debug state. AU 9 0 9:0 Reserved, RES0. When FEAT_AMU_EXT64 is implemented Accessible at offset 0xE04 from AMU When FEAT_AMU_EXT32 is implemented Accessible at offset 0xE10 from AMU When FEAT_AMU_EXT64 is implemented 2026-03-26 20:27:25 2026-03_rel