AMDEVAFF0 Activity Monitors Device Affinity Register 0 It is IMPLEMENTATION DEFINED whether AMDEVAFF0 is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented, FEAT_AMU_EXT32 is implemented, and an implementation implements AMDEVAFF0 AMU 0xFA8 When ImpDefBool("AMU CoreSight management registers ignore access controls") RO When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the AMU component relates to. AMU AMDEVAFF0 is a 32-bit register. 31 31 31 Reserved, RAO/WI. U 30 30 30 Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. 0b0 Processor is part of a multiprocessor system. 0b1 Processor is part of a uniprocessor system. RO 29 25 29:25 Reserved, RES0. MT 24 24 24 Indicates whether the lowest level of affinity consists of logical PEs that are implemented using an interdependent approach, such as multithreading. See the description of Aff0 for more information about affinity levels. This field does not indicate that multithreading is implemented and does not indicate that PEs with different affinity level 0 values, and the same values for affinity level 1 and higher are implemented. 0b0 Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is largely independent. 0b1 Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is very interdependent. RO Aff2 23 16 23:16 Affinity level 2. See the description of Aff0 for more information. This field has an IMPLEMENTATION DEFINED value. RO Aff1 15 8 15:8 Affinity level 1. See the description of Aff0 for more information. This field has an IMPLEMENTATION DEFINED value. RO Aff0 7 0 7:0 Affinity level 0. The value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole. This field has an IMPLEMENTATION DEFINED value. RO Accessible at offset 0xFA8 from AMU 2026-03-26 20:27:25 2026-03_rel