AMDEVARCH Activity Monitors Device Architecture Register It is IMPLEMENTATION DEFINED whether AMDEVARCH is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented, an implementation implements AMDEVARCH, and FEAT_AMU_EXT is implemented AMU 0xFBC When ImpDefBool("AMU CoreSight management registers ignore access controls") RO When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMU 0xFBC When ImpDefBool("AMU CoreSight management registers ignore access controls") RO When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO Identifies the programmers' model architecture of the AMU component. AMU AMDEVARCH is a 32-bit register. ARCHITECT 31 21 31:21 Defines the architect of the component. For Activity Monitors, this is Arm Limited. Bits [31:28] are the JEP106 continuation code, 0b0100. Bits [27:21] are the JEP106 identification code, 0b0111011. Reads as 0b01000111011. RO PRESENT 20 20 20 DEVARCH present. Indicates that the AMDEVARCH register is present. Reads as 0b1. RO REVISION 19 16 19:16 Defines the architecture revision. For architectures defined by Arm this is the minor revision. All other values are reserved. 0b0000 Architecture revision is AMUv1. RO ARCHID 15 0 15:0 Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided. For AMU: Bits [15:12] are the architecture version, also identified as AMDEVARCH.ARCHVER. Bits [11:0] are the architecture part number, also identified as AMDEVARCH.ARCHPART. AMDEVARCH.ARCHVER = 0x0, which corresponds to AMU architecture version AMUv1. If FEAT_AMU_EXT32 is implemented, AMDEVARCH is 0xA66. If FEAT_AMU_EXT64 is implemented, AMDEVARCH is 0xA67. 0x0A66 AMUv1, with FEAT_AMU_EXT32 implemented. 0x0A67 AMUv1, with FEAT_AMU_EXT64 implemented. RO Accessible at offset 0xFBC from AMU When FEAT_AMU_EXT64 is implemented Accessible at offset 0xFBC from AMU When FEAT_AMU_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel