AMEVCNTR0<n> Activity Monitors Event Counter Registers 0 It is IMPLEMENTATION DEFINED whether AMEVCNTR0<n> is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented 0 3 AMU 0x000 + (8 * n) When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMU 0x000 + (8 * n) When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {'001', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {'010', '000'} RAZ/WI When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != '011' RAZ/WI When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == '0' RAZ/WI RO AMEVCNTR0<n>_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 AMEVCNTR0<n> Architectural AArch32 31 0 31 0 31 0 31 0 Provides access to the architected activity monitor event counters. AMU AMEVCNTR0<n> is a 64-bit register. ACNT 63 0 63:0 Architected activity monitor event counter n. Value of architected activity monitor event counter n, where n is the number of this register and is a number from 0 to 3. 0x0000000000000000 If <n> is greater than or equal to the number of architected activity monitor event counters, reads of AMEVCNTR0<n> are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'. AMCGCR.CG0NC identifies the number of architected activity monitor event counters. [63:0] Accessible at offset 0x000 + (8 * n) from AMU When FEAT_AMU_EXT64 is implemented [63:0] Accessible at offset 0x000 + (8 * n) from AMU When FEAT_AMU_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel