AMROOTCR Activity Monitors Root Control Register It is IMPLEMENTATION DEFINED whether AMROOTCR is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMU_EXTACR is implemented and FEAT_RME is implemented AMU 0xE48 When an access is Root RW RAZ/WI Control register for Root, Realm, Secure, and Non-secure access to External AMU registers. AMU AMROOTCR is a 64-bit register. 63 32 63:32 Reserved, RES0. IMPL 31 31 31 0b1 Indicates AMROOTCR is present. RAO/WI 30 7 30:7 Reserved, RES0. RA 6 4 6:4 Register Access to all External Activity Monitors registers. Other values are reserved. For the CoreSight management registers, 0xFA8 to 0xFFC, it is IMPLEMENTATION DEFINED whether these registers are RO or RAZ/WI when register access is disabled by this field. 0b000 Root register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. 0b001 Root and Realm register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. 0b010 Root and Secure register access is enabled. Access from other address spaces is disabled, meaning accesses to all External AMU registers are RAZ/WI. 0b011 Root, Secure, Non-secure and Realm register access is enabled. 3 0 3:0 Reserved, RES0. Accessible at offset 0xE48 from AMU 2026-03-26 20:27:25 2026-03_rel