AMSCR Activity Monitors Secure Control Register It is IMPLEMENTATION DEFINED whether AMSCR is implemented in the Core power domain or in the Debug power domain AMU when FEAT_AMU_EXTACR is implemented and FEAT_RME is not implemented AMU 0xE40 When an access is Secure or an access is Root RW RAZ/WI Control register for Secure, and Non-secure access to External AMU registers. AMU AMSCR is a 64-bit register. 63 32 63:32 Reserved, RES0. IMPL 31 31 31 0b1 Indicates AMSCR is present. RAO/WI 30 2 30:2 Reserved, RES0. NSRA 1 1 1 Register Access to all External Activity Monitors registers. 0b0 Non-secure access is disabled, RAZ/WI. 0b1 Non-Secure access is enabled. 0 0 0 Reserved, RES0. Accessible at offset 0xE40 from AMU 2026-03-26 20:27:25 2026-03_rel