<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>ASICCTL</reg_short_name>
        
        <reg_long_name>CTI External Multiplexer Control register</reg_long_name>

        <power_domain_text>It is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether ASICCTL is implemented in the Core power domain or in the Debug power domain</power_domain_text>


      
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>CTI</reg_component>
    <reg_offset><hexnumber>0x144</hexnumber></reg_offset>
    <reg_instance>ASICCTL</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalDebugAccess(addrdesc), and SoftwareLockStatus(addrdesc)</reg_access_level>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>IMPDEF</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Can be used to provide <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> controls for the CTI. For example, the register might be used to control multiplexors for additional <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> triggers. The <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> controls provided by this register might modify the architecturally defined behavior of the CTI.</para>

      </purpose_text>
      <purpose_text>
        <note><para>The architecturally-defined triggers must not be multiplexed.</para></note>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>CTI</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>If it is implemented in the Core power domain, then it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether it is in the Cold reset domain or the Warm reset domain.</para>

      </configuration_text>
      <configuration_text>
        <para>This register must reset to a value that supports the architecturally-defined behavior of the CTI. Changing the value of the register from its reset value causes <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> behavior that might differ from the architecturally-defined behavior of the CTI.</para>

      </configuration_text>
      <configuration_text>
        <para>Other than the requirements listed in this register description, all aspects of the reset behavior of the ASICCTL are <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>ASICCTL is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>IMPLEMENTATION DEFINED</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>