CNTACR<n> Counter-timer Access Control Registers It is IMPLEMENTATION DEFINED whether CNTACR<n> is implemented in the Core power domain or in the Debug power domain 0 7 Timer CNTCTLBase 0x040 + (4 * n) CNTACR<n> RW Provides top-level access controls for the elements of a timer frame. CNTACR<n> provides the controls for frame CNTBaseN. In addition to the CNTACR<n> control: CNTNSAR controls whether CNTACR<n> is accessible by Non-secure accesses. If frame CNTEL0BaseN is implemented, the CNTEL0ACR in frame CNTBaseN provides additional control of accesses to frame CNTEL0BaseN. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. Implemented only if the value of CNTTIDR.Frame<n> is 1. An implementation of the counters might not provide configurable access to some or all of the features. In this case, the associated field in the CNTACR<n> register is: RAZ/WI if access is always denied. RAO/WI if access is always permitted. CNTACR<n> is a 32-bit register. 31 6 31:6 Reserved, RES0. RWPT 5 5 5 Read/write access to the EL1 Physical Timer registers CNTP_CVAL, CNTP_TVAL, and CNTP_CTL, in frame <n>. 0b0 No access to the EL1 Physical Timer registers in frame <n>. The registers are RES0. 0b1 Read/write access to the EL1 Physical Timer registers in frame <n>. AU RWVT 4 4 4 Read/write access to the Virtual Timer register CNTV_CVAL, CNTV_TVAL, and CNTV_CTL, in frame <n>. 0b0 No access to the Virtual Timer registers in frame <n>. The registers are RES0. 0b1 Read/write access to the Virtual Timer registers in frame <n>. AU RVOFF 3 3 3 Read-only access to CNTVOFF, in frame <n>. 0b0 No access to CNTVOFF in frame <n>. The register is RES0. 0b1 Read-only access to CNTVOFF in frame <n>. AU RFRQ 2 2 2 Read-only access to CNTFRQ, in frame <n>. 0b0 No access to CNTFRQ in frame <n>. The register is RES0. 0b1 Read-only access to CNTFRQ in frame <n>. AU RVCT 1 1 1 Read-only access to CNTVCT, in frame <n>. 0b0 No access to CNTVCT in frame <n>. The register is RES0. 0b1 Read-only access to CNTVCT in frame <n>. AU RPCT 0 0 0 Read-only access to CNTPCT, in frame <n>. 0b0 No access to CNTPCT in frame <n>. The register is RES0. 0b1 Read-only access to CNTPCT in frame <n>. AU In a system that supports the Realm Management Extension, CNTNSAR.NS<n> describes how these registers can be accessed by Root or Realm accesses. In a system that recognizes two Security states: CNTACR<n> is always accessible by Secure accesses. CNTNSAR.NS<n> determines whether CNTACR<n> is accessible by Non-secure accesses. 2026-03-26 20:27:25 2026-03_rel