CNTCR Counter Control Register It is IMPLEMENTATION DEFINED whether CNTCR is implemented in the Core power domain or in the Debug power domain Timer CNTControlBase 0x000 CNTCR RW Enables the counter, controls the counter resolution, and controls counter behavior during debug. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. CNTCR is a 32-bit register. 31 18 31:18 Reserved, RES0. FCREQ 17 8 17:8 Frequency change request. Indicates the number of the entry in the Frequency modes table to select. Selecting an unimplemented entry, or an entry that contains 0, has no effect on the counter. The maximum number of entries in the Frequency modes table is IMPLEMENTATION DEFINED up to a maximum of 1004 entries, see 'The Frequency modes table'. An implementation is only required to implement an FCREQ field that can hold values from 0 to the highest supported Frequency modes table entry. Any unrequired most-significant bits of FCREQ can be implemented as RES0. 0x0 7 3 7:3 Reserved, RES0. SCEN 2 2 0 Scale Enable. The SCEN bit can only be changed when the counter is disabled, when CNTCR.EN == 0. If the value of CNTCR.SCEN changes when CNTCR.EN == 1, then: The counter value becomes UNKNOWN. The counter value remains UNKNOWN on future ticks of the clock. When the CNTCV register in the CNTControlBase frame of the memory mapped counter module is written to, the accumulated fraction information is reset to zero. 0b0 Scaling is not enabled. The counter value is incremented by 0x1.0000000 for each counter tick. 0b1 Scaling is enabled. The counter is incremented by CNTSCR.ScaleVal for each counter tick. AU When FEAT_CNTSC is implemented 2 2 2 Reserved, RES0. Otherwise HDBG 1 1 1 Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter: 0b0 System counter ignores Halt-on-debug. 0b1 Asserted Halt-on-debug signal halts system counter update. AU EN 0 0 0 Enables the counter: 0b0 System counter disabled. 0b1 System counter enabled. '0' In a system that supports the Realm Management Extension, the CNTControlBase frame, which includes this register, is implemented only in the Root physical address space. In a system that supports Secure and Non-secure physical address spaces, the CNTControlBase frame, which includes this register, is implemented only in the Secure physical address space. 2026-03-26 20:27:25 2026-03_rel