CNTFID<n> Counter Frequency IDs, n > 0 It is IMPLEMENTATION DEFINED whether CNTFID<n> is implemented in the Core power domain or in the Debug power domain 1 1003 Timer CNTControlBase 0x020 + (4 * n) CNTFID<n> RO or RW Indicates alternative system counter frequencies. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. The possible frequencies for the system counter are stored in the Frequency modes table as 32-bit words starting with the base frequency, CNTFID0, see 'The Frequency modes table'. The number of CNTFID<n> registers is IMPLEMENTATION DEFINED, and the only required CNTFID<n> register is CNTFID0. The final entry in the Frequency modes table must be followed by a 32-bit word of zero value, to mark the end of the table. The architecture can support up to 1004 entries in the Frequency modes table, including the zero-word end marker, and the number of entries is IMPLEMENTATION DEFINED up to this limit. For an implementation that includes registers in the IMPLEMENTATION DEFINED register space 0x0C0-0x0FC, the maximum number of entries in the Frequency modes table is 40, including the zero-word end marker. Typically, the Frequency modes table will be in read-only memory. However, a system implementation might use read/write memory for the table, and initialize the table entries as part of its start-up sequence. If the Frequency modes table is in read/write memory, Arm strongly recommends that the table is not updated once the system is running. CNTFID<n> is a 32-bit register. Frequency 31 0 31:0 A system counter frequency, in Hz. Must be an exact divisor of the base frequency. Arm strongly recommends that all frequency values in the Frequency modes table are integer power-of-two divisors of the base frequency. When the system timer is operating at a lower frequency than the base frequency, the increment applied at each counter update is increased by the ratio of the base frequency and the selected frequency. AU It is IMPLEMENTATION DEFINED whether this register is RO or RW In a system that supports the Realm Management Extension, the CNTControlBase frame, which includes these registers, is implemented only in the Root physical address space. In a system that supports Secure and Non-secure physical address spaces, the CNTControlBase frame, which includes these registers, is implemented only in the Secure physical address space. 2026-03-26 20:27:25 2026-03_rel