<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>CNTFRQ</reg_short_name>
        
        <reg_long_name>Counter-timer Frequency</reg_long_name>

        <power_domain_text>It is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CNTFRQ is implemented in the Core power domain or in the Debug power domain</power_domain_text>


      
      

    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>Timer</reg_component>
    <reg_frame>CNTBaseN</reg_frame>
    <reg_offset><hexnumber>0x010</hexnumber></reg_offset>
    <reg_instance>CNTFRQ</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>Timer</reg_component>
    <reg_frame>CNTEL0BaseN</reg_frame>
    <reg_offset><hexnumber>0x010</hexnumber></reg_offset>
    <reg_instance>CNTFRQ</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>Timer</reg_component>
    <reg_frame>CNTCTLBase</reg_frame>
    <reg_offset><hexnumber>0x000</hexnumber></reg_offset>
    <reg_instance>CNTFRQ</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>This register is provided so that software can discover the <xref linkend="#effective_frequency">effective frequency</xref> of the system counter. The instance of the register in the CNTCTLBase frame must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Timer</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>For more information see <xref linkend="#CEGHAIAF">'Power and reset domains for the system level implementation of the Generic Timer'</xref>.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CNTFRQ is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ClockFreq</field_name>
    <field_shortdesc>Clock frequency</field_shortdesc>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para>Clock frequency. Indicates the <xref linkend="#effective_frequency">effective frequency</xref> of the system counter, in Hz.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Timer">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>CNTFRQ must be implemented as an RW register in the CNTCTLBase frame.</para>

      </access_permission_text>
      <access_permission_text>
        <para>In a system that supports the Realm Management Extension, the instance of the register in the CNTCTLBase frame is accessible as follows:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>For Root accesses, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether accesses to the register are permitted or behave as <arm-defined-word>RES0</arm-defined-word>.</content>
</listitem><listitem><content>For Realm accesses, this register behaves as <arm-defined-word>RES0</arm-defined-word>.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>In a system that recognizes two Security states, the instance of the register in the CNTCTLBase frame is only accessible by Secure accesses.</para>

      </access_permission_text>
      <access_permission_text>
        <para>CNTFRQ can be implemented as a RO register in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.</para>

      </access_permission_text>
      <access_permission_text>
        <para><xref linkend="#CEGDFJAG">'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames'</xref> describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>Whether the CNTBaseN frame has virtual timer capability.</content>
</listitem><listitem><content>Whether the corresponding CNTEL0BaseN frame is implemented.</content>
</listitem><listitem><content>For an implementation that supports the Realm Management Extension, whether the CNTBaseN frame, and any corresponding CNTEL0BaseN frame, is accessible by Root and Realm accesses.</content>
</listitem><listitem><content>For an implementation that recognizes two Security states, whether the CNTBaseN frame, and any corresponding CNTEL0BaseN frame, is accessible by Non-secure accesses. The CNTBaseN frame is always accessible by Secure accesses.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>For an implemented CNTBaseN frame:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>CNTFRQ is accessible in that frame, as a RO register, if the value of <register_link state="ext" id="ext-cntacrn.xml">CNTACR&lt;n&gt;</register_link>.RFRQ is 1.</content>
</listitem><listitem><content>Otherwise, the CNTFRQ address in that frame is RAZ/WI.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>For an implemented CNTEL0BaseN frame:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>CNTFRQ is accessible as a RO register in that frame if both:<list type="unordered">
<listitem><content>CNTFRQ is accessible in the corresponding CNTBaseN frame.</content>
</listitem><listitem><content>Either the value of <register_link state="ext" id="ext-cntel0acr.xml">CNTEL0ACR</register_link>.EL0VCTEN is 1 or the value of <register_link state="ext" id="ext-cntel0acr.xml">CNTEL0ACR</register_link>.EL0PCTEN is 1.</content>
</listitem></list>
</content>
</listitem><listitem><content>Otherwise, the CNTFRQ address in that frame is RAZ/WI.</content>
</listitem></list>
      </access_permission_text>





    
    
    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>