CNTNSAR Counter-timer Non-secure Access Register It is IMPLEMENTATION DEFINED whether CNTNSAR is implemented in the Core power domain or in the Debug power domain Timer CNTCTLBase 0x004 CNTNSAR RW Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. CNTNSAR is a 32-bit register. 31 8 31:8 Reserved, RES0. NS<n> 7 0 7:0 Non-secure access to frame n. This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses. If frame CNTBase<n>: Is not implemented, then NS<n> is RES0. Is not Configurable access, and is accessible only by Secure accesses, then NS<n> is RES0. Is not Configurable access, and is accessible by both Secure and Non-secure accesses, then NS<n> is RES1. 7 0 0b0 Secure access only. Behaves as RES0 to Non-secure accesses. If FEAT_RME is implemented, it is IMPLEMENTATION DEFINED whether Root accesses to the specified registers are permitted or behave as RES0. For Realm accesses, the specified registers behave as RES0. 0b1 Secure and Non-secure accesses permitted. If FEAT_RME is implemented, it is IMPLEMENTATION DEFINED whether Root and Realm accesses to the specified registers are permitted. If not permitted, the specified registers behave as RES0 for Root and Realm accesses. AU In a system that supports the Realm Management Extension, this register is accessible as follows: For Root accesses, it is IMPLEMENTATION DEFINED whether accesses to the register are permitted or behave as RES0. For Realm accesses, this register behaves as RES0. In a system that recognizes two Security states, this register is only accessible by Secure accesses. 2026-03-26 20:27:25 2026-03_rel