CNTSCR Counter Scale Register It is IMPLEMENTATION DEFINED whether CNTSCR is implemented in the Core power domain or in the Debug power domain when FEAT_CNTSC is implemented Timer CNTControlBase 0x10 CNTSCR RW Enables the counter, controls the counter effective frequency setting, and controls counter behavior during debug. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. CNTSCR is a 32-bit register. ScaleVal 31 0 31:0 Scale Value When counter scaling is enabled, ScaleVal is the average amount added to the counter value for one period of the frequency of the Generic counter as described in the CNTFRQ register. The actual rate of update of the counter value is determined by the counter resolution. ScaleVal is expressed as an unsigned fixed point number with an 8-bit integer value and a 24-bit fractional value. CNTSCR.ScaleVal can only be changed when CNTCR.EN == 0. If the value of this field is changed when CNTCR.EN == 1: The counter value becomes UNKNOWN. The counter value remains UNKNOWN on future ticks of the clock. AU In a system that supports the Realm Management Extension, the CNTControlBase frame, which includes this register, is implemented only in the Root physical address space. In a system that supports Secure and Non-secure physical address spaces, the CNTControlBase frame, which includes this register, is implemented only in the Secure physical address space. 2026-03-26 20:27:25 2026-03_rel