CNTSR Counter Status Register It is IMPLEMENTATION DEFINED whether CNTSR is implemented in the Core power domain or in the Debug power domain Timer CNTControlBase 0x004 CNTSR RO Provides counter resolution status information. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. CNTSR is a 32-bit register. 31 18 31:18 Reserved, RES0. FCACK 17 8 17:8 Frequency Change Acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table'. 0x000000 7 2 7:2 Reserved, RES0. DBGH 1 1 1 Indicates whether the counter is halted because the Halt-on-debug signal is asserted: 0b0 Counter is not halted. 0b1 Counter is halted. AU 0 0 0 Reserved, RES0. In a system that supports the Realm Management Extension, the CNTControlBase frame, which includes this register, is implemented only in the Root physical address space. In a system that supports Secure and Non-secure physical address spaces, the CNTControlBase frame, which includes this register, is implemented only in the Secure physical address space. 2026-03-26 20:27:25 2026-03_rel