CNTTIDR
Counter-timer Timer ID Register
It is IMPLEMENTATION DEFINED whether CNTTIDR is implemented in the Core power domain or in the Debug power domain
Timer
CNTCTLBase
0x008
CNTTIDR
RO
Indicates the implemented timers in the physical address space, and their features. For each value of N from 0 to 7 it indicates whether:
Frame CNTBaseN is a view of an implemented timer.
Frame CNTBaseN has a second view, CNTEL0BaseN.
Frame CNTBaseN has a virtual timer capability.
Timer
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTTIDR is a 32-bit register.
Frame<n>
31
0
31:0
A 4-bit field indicating the features of frame CNTBase<n>.
Bit[3] of the field is RES0.
Bit[2], the FEL0 subfield, indicates whether frame CNTBase<n> has a second view, CNTEL0Base<n>. The possible values of this bit are:
Bit[2]Meaning
0b0Frame<n> does not have a second view. The CNTEL0ACR register in the first view of the frame is RES0.
0b1Frame<n> has a second view, CNTEL0Base<n>.
If bit[0] is 0, bit[2] is RES0.
Bit[1], the FVI subfield, indicates whether both:
Frame CNTBase<n> implements the virtual timer registers CNTV_CVAL, CNTV_TVAL, and CNTV_CTL.
This CNTCTLBase frame implements the virtual timer offset register CNTVOFF<n>.
The possible values of bit[1] are:
Bit[1]Meaning
0b0Frame<n> does not have virtual capability. The virtual time and offset registers are RES0.
0b1Frame<n> has virtual capability. The virtual time and offset registers are implemented.
If bit[0] is 0, bit[1] is RES0.
Bit[0], the FI subfield, indicates whether frame CNTBase<n> is implemented. The possible values of this bit are:
Bit[0]Meaning
0b0Frame<n> is not implemented. All registers associated with the frame are RES0.
0b1Frame<n> is implemented.
7
0
In a system that supports the Realm Management Extension, it is IMPLEMENTATION DEFINED whether Root and Realm accesses to this register are permitted. If not permitted, this register behaves as RES0 for Root and Realm accesses.
In a system that recognizes two Security states, this register is accessible by both Secure and Non-secure accesses.
2026-03-26 20:27:25
2026-03_rel