CNTVOFF<n> Counter-timer Virtual Offsets It is IMPLEMENTATION DEFINED whether CNTVOFF<n> is implemented in the Core power domain or in the Debug power domain Implementation of this register is OPTIONAL. 0 7 Timer CNTCTLBase 0x080 + (8 * n) RW Timer CNTCTLBase 0x084 + (8 * n) RW Holds the 64-bit virtual offset for frame CNTBase<n>. This is the offset between real time and virtual time. Timer For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'. CNTVOFF<n> is a 64-bit register. VOffset Virtual offset 63 0 63:0 Virtual offset. AU In the CNTCTLBase frame a CNTVOFF<n> register must be implemented, as a RW register, for each CNTBaseN frame that has virtual timer capability. For more information, see 'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames'. The value of <n> in an instance of CNTVOFF<n> specifies the value of N for the associated CNTBaseN frame. In a system that supports the Realm Management Extension, CNTNSAR.NS<n> describes how these registers can be accessed by Root or Realm accesses. In a system that recognizes two Security states, for any CNTVOFF<n> register in the CNTCTLBase frame: CNTVOFF<n> is always accessible by Secure accesses. CNTNSAR.NS<n> determines whether CNTVOFF<n> is accessible by Non-secure accesses. The register location of any unimplemented CNTVOFF<n> register in the CNTCTLBase frame is RAZ/WI. The CNTVOFF<n> register is accessible in the CNTBaseN frame using CNTVOFF. In an implementation that supports 64-bit atomic accesses, then the CNTVOFF<n> registers must be accessible as atomic 64-bit values. 2026-03-26 20:27:25 2026-03_rel