<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
<!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<!--The data contained in this document is preliminary and subject to change or correction following further review. -->
<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>CTICIDR3</reg_short_name>
        
        <reg_long_name>CTI Component Identification Register 3</reg_long_name>

        <power_domain_text>CTICIDR3 is in the Debug power domain</power_domain_text>


      
          <reg_condition otherwise="RES0" verbatim="True"><para>Implementation of this register is <arm-defined-word>OPTIONAL</arm-defined-word>.</para></reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>CTI</reg_component>
    <reg_offset><hexnumber>0xFFC</hexnumber></reg_offset>
    <reg_instance>CTICIDR3</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides information to identify a CTI component.</para>

      </purpose_text>
      <purpose_text>
        <para>For more information, see <xref linkend="#BABBFIID">'About the Component Identification scheme'</xref>.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>CTI</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>This register is required for CoreSight compliance.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CTICIDR3 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>31:8</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-7_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PRMBL_3</field_name>
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>Preamble.</para>
    </field_description>
    <field_description order="after">
      <para>Reads as <hexnumber>0xB1</hexnumber>.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_8" msb="31" lsb="8"/>
  <fieldat id="fieldset_0-7_0" msb="7" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>