CTIDEVARCH CTI Device Architecture register CTIDEVARCH is in the Debug power domain CTI 0xFBC CTIDEVARCH RO Identifies the programmers' model architecture of the CTI component. CTI If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory. Arm recommends that the CTI is CTIv2. In an Armv8.5 compliant implementation, the CTI must be CTIv2. If this register is not implemented, CTIDEVAFF0 and CTIDEVAFF1 are also not implemented. CTIDEVARCH is a 32-bit register. ARCHITECT 31 21 31:21 Defines the architect of the component. For CTI, this is Arm Limited. Bits [31:28] are the JEP106 continuation code, 0b0100. Bits [27:21] are the JEP106 identification code, 0b0111011. Reads as 0b01000111011. RO PRESENT 20 20 20 DEVARCH present. Indicates that the CTIDEVARCH register is present. Reads as 0b1. RO REVISION 19 16 19:16 Revision. Defines the architecture revision of the component. All other values are reserved. When FEAT_DoPD is implemented, the value 0b0000 is not permitted. 0b0000 First revision. 0b0001 As 0b0000, and also adds support for CTIDEVCTL. RO ARCHID 15 0 15:0 Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided. For CTI: Bits [15:12] are the architecture version, 0x1. Bits [11:0] are the architecture part number, 0xA14. This corresponds to CTI architecture version CTIv2. Reads as 0x1A14. RO 2026-03-26 20:27:25 2026-03_rel