<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>CTIITCTRL</reg_short_name>
        
        <reg_long_name>CTI Integration mode Control register</reg_long_name>

        <power_domain_text>The power domain of CTIITCTRL is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word></power_domain_text>


      
          <reg_condition otherwise="RES0" verbatim="True"><para>Implementation of this register is <arm-defined-word>OPTIONAL</arm-defined-word>.</para></reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>CTI</reg_component>
    <reg_offset><hexnumber>0xF00</hexnumber></reg_offset>
    <reg_instance>CTIITCTRL</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus()</reg_access_level>
          <reg_access_type>IMPDEF</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_level>When SoftwareLockStatus(addrdesc)</reg_access_level>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Enables the CTI to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>CTI</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>CTIITCTRL is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>1</field_lsb>
    <rel_range>31:1</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-0_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>IME</field_name>
    <field_msb>0</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection.</para>
    </field_description>
    <field_description order="after">
      <para>The integration mode behavior is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Normal operation.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Integration mode enabled.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset>
        <field_reset_special_text><para>The following resets apply:</para>
<list type="unordered">
<listitem><content>
<para>If the register is implemented in the Core power domain:</para>
<list type="unordered">
<listitem><content>On a Cold reset, this field resets to 0.</content>
</listitem><listitem><content>On an External debug reset, the value of this field is unchanged.</content>
</listitem><listitem><content>On a Warm reset, the value of this field is unchanged.</content>
</listitem></list>
</content>
</listitem><listitem><content>
<para>If the register is implemented in the External debug power domain:</para>
<list type="unordered">
<listitem><content>On a Cold reset, the value of this field is unchanged.</content>
</listitem><listitem><content>On an External debug reset, this field resets to 0.</content>
</listitem><listitem><content>On a Warm reset, the value of this field is unchanged.</content>
</listitem></list>
</content>
</listitem></list></field_reset_special_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_1" msb="31" lsb="1"/>
  <fieldat id="fieldset_0-0_0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>