DBGBVR<n>_EL1 Debug Breakpoint Value Registers DBGBVR<n>_EL1 is in the Core power domain 0 63 Debug 0x400 + (16 * n) DBGBVR<n>_EL1 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus(), or !AllowExternalDebugAccess(addrdesc) ERROR When SoftwareLockStatus(addrdesc) RO RW DBGBVR<n>_EL1 Architectural AArch64 63 0 63 0 63 0 63 0 DBGBVR<n> Architectural AArch32 31 0 31 0 31 0 31 0 DBGBXVR<n> Architectural AArch32 63 32 31 0 63 32 31 0 Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1. Debug How this register is interpreted depends on the value of DBGBCR<n>_EL1.BT. When DBGBCR<n>_EL1.BT is 0b0x0x, this register holds a virtual address. When DBGBCR<n>_EL1.BT is 0b001x, 0b011x, or 0b110x, this register holds a Context ID. When DBGBCR<n>_EL1.BT is 0b100x, this register holds a VMID. When DBGBCR<n>_EL1.BT is 0b101x, this register holds a VMID and a Context ID. When DBGBCR<n>_EL1.BT is 0b111x, this register holds two Context ID values. For other values of DBGBCR<n>_EL1.BT, this register is RES0. If breakpoint n is not implemented, then accesses to this register are: RES0 when IsCorePowered() && !DoubleLockStatus() && !OSLockStatus() && AllowExternalDebugAccess(). A CONSTRAINED UNPREDICTABLE choice of RES0 or ERROR otherwise. DBGBVR<n>_EL1 is a 64-bit register. When DBGBCR<n>_EL1.BT IN {'0x0x'} DBGBCR<n>_EL1.BT==0b0x0x RESS[14:8] 63 57 63:57 Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1. Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether: The bits are hardwired to a copy of the most significant bit of VA, meaning writes to these bits are ignored, and reads to the bits always return the hardwired value. The value in those bits can be written, and reads will return the last value written. The value held in those bits is ignored by hardware. VA[56:53] 56 53 3:0 Extension to VA[48:2]. For more information, see VA[48:2]. AU When FEAT_LVA3 is implemented RESS[7:4] 56 53 3:0 Extension to RESS[14:8]. For more information, see RESS[14:8]. Otherwise VA[52:49] 52 49 3:0 Extension to VA[48:2]. For more information, see VA[48:2]. AU When FEAT_LVA is implemented RESS[3:0] 52 49 3:0 Extension to RESS[14:8]. For more information, see RESS[14:8]. Otherwise VA[48:2] 48 2 48:2 If the address is being matched in an AArch64 stage 1 translation regime: This field contains bits[48:2] of the address for comparison. When FEAT_LVA3 is implemented, (VA[56:53]:VA[52:49]) forms the upper part of the address value. If FEAT_LVA3 is not implemented, bits VA[56:53] are part of the RESS field. When FEAT_LVA is implemented, VA[52:49] forms the upper part of the address value. If FEAT_LVA is not implemented, bits [52:49] are part of the RESS field. If the address is being matched in an AArch32 stage 1 translation regime, the first 20 bits of this field are RES0, and the rest of the field contains bits[31:2] of the address for comparison. AU 1 0 1:0 Reserved, RES0. When DBGBCR<n>_EL1.BT IN {'001x'} DBGBCR<n>_EL1.BT==0b001x 63 32 63:32 Reserved, RES0. ContextID 31 0 31:0 Context ID value for comparison. The value is compared against CONTEXTIDR_EL2 when the Effective value of HCR_EL2.E2H is 1, and either: The PE is executing at EL2. HCR_EL2.TGE is 1, the PE is executing at EL0, and EL2 is enabled in the current Security state. Otherwise, the value is compared against the following: CONTEXTIDR when the PE is executing at AArch32. CONTEXTIDR_EL1 when the PE is executing at AArch64. AU When DBGBCR<n>_EL1.BT IN {'011x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented DBGBCR<n>_EL1.BT==0b011x, EL2 is implemented, and FEAT_Debugv8p1 is implemented 63 32 63:32 Reserved, RES0. ContextID 31 0 31:0 Context ID value for comparison against CONTEXTIDR_EL1. AU When DBGBCR<n>_EL1.BT IN {'100x'} and EL2 is implemented DBGBCR<n>_EL1.BT==0b100x and EL2 is implemented 63 48 63:48 Reserved, RES0. VMID[15:8] 47 40 7:0 Extension to VMID[7:0]. For more information, see DBGBVR<n>_EL1.VMID[7:0]. If EL2 is using AArch32, this field is RES0. AU When FEAT_VMID16 is implemented and VTCR_EL2.VS == '1' 47 40 47:40 Reserved, RES0. Otherwise VMID[7:0] 39 32 39:32 VMID value for comparison. The VMID is 8 bits when any of the following are true: EL2 is using AArch32. VTCR_EL2.VS is 0. FEAT_VMID16 is not implemented. AU 31 0 31:0 Reserved, RES0. When DBGBCR<n>_EL1.BT IN {'101x'} and EL2 is implemented DBGBCR<n>_EL1.BT==0b101x and EL2 is implemented 63 48 63:48 Reserved, RES0. VMID[15:8] 47 40 7:0 Extension to VMID[7:0]. For more information, see DBGBVR<n>_EL1.VMID[7:0]. If EL2 is using AArch32, or if the implementation has an 8-bit VMID, this field is RES0. AU When FEAT_VMID16 is implemented and VTCR_EL2.VS == '1' 47 40 47:40 Reserved, RES0. Otherwise VMID[7:0] 39 32 39:32 VMID value for comparison. The VMID is 8 bits when any of the following are true: EL2 is using AArch32. VTCR_EL2.VS is 0. FEAT_VMID16 is not implemented. AU ContextID 31 0 31:0 Context ID value for comparison against CONTEXTIDR_EL1. AU When DBGBCR<n>_EL1.BT IN {'110x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented DBGBCR<n>_EL1.BT==0b110x and EL2 is implemented ContextID2 63 32 63:32 Context ID value for comparison against CONTEXTIDR_EL2. AU 31 0 31:0 Reserved, RES0. When DBGBCR<n>_EL1.BT IN {'111x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented DBGBCR<n>_EL1.BT==0b111x and EL2 is implemented ContextID2 63 32 63:32 Context ID value for comparison against CONTEXTIDR_EL2. AU ContextID 31 0 31:0 Context ID value for comparison against CONTEXTIDR_EL1. AU When DBGBCR<n>_EL1.BT IN {'0x0x'} When DBGBCR<n>_EL1.BT IN {'001x'} When DBGBCR<n>_EL1.BT IN {'011x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented When DBGBCR<n>_EL1.BT IN {'100x'} and EL2 is implemented When DBGBCR<n>_EL1.BT IN {'101x'} and EL2 is implemented When DBGBCR<n>_EL1.BT IN {'110x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented When DBGBCR<n>_EL1.BT IN {'111x'}, EL2 is implemented, and FEAT_Debugv8p1 is implemented 2026-03-26 20:27:25 2026-03_rel