DBGDTRRX_EL0 Debug Data Transfer Register, Receive DBGDTRRX_EL0 is in the Core power domain Debug 0x080 DBGDTRRX_EL0 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW DBGDTRRX_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 DBGDTRRXint Architectural AArch32 31 0 31 0 31 0 31 0 Transfers data from an external debugger to the PE. For example, it is used by a debugger transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communications Channel. Debug DBGDTRRX_EL0 is a 32-bit register. DTRRX Update DTRRX 31 0 31:0 Update DTRRX. Writes to this register: If RXfull is 0, update the value in DTRRX and set RXfull to 1. If RXfull is 1, the written value is ignored and RXO is set to 1. Reads of this register return the last value written to DTRRX and do not change RXfull. For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'. AU If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in Memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following: It must complete execution in Debug state before the PE executes the restart sequence. It must complete execution in Non-debug state before the PE executes the restart sequence. It must be abandoned. This means that the instruction does not execute. Any registers or memory accessed by the instruction are left in an UNKNOWN state. 2026-03-26 20:27:25 2026-03_rel