EDAA32PFR External Debug Auxiliary Processor Feature Register Debug 0xD60 EDAA32PFR When IsCorePowered() and !DoubleLockStatus() RO When FEAT_DoPD is implemented and !IsCorePowered() ERROR IMPDEF Provides information about implemented PE features. The register mnemonic, EDAA32PFR, is derived from previous definitions of this register that defined this register only when AArch64 was not supported. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers EDAA32PFR is a 64-bit register. 63 20 63:20 Reserved, RES0. MSA_frac 19 16 3:0 Memory System Architecture fractional field. This holds the information on additional Memory System Architectures supported. All other values are reserved. 0b0001 PMSAv8-64 supported in all translation regimes. VMSAv8-64 not supported. 0b0010 PMSAv8-64 supported in all translation regimes. In addition to PMSAv8-64, stage 1 EL1&0 translation regime also supports VMSAv8-64. RO When EDAA32PFR.PMSA == '0000' and EDAA32PFR.VMSA == '1111' 19 16 19:16 Reserved, RES0. Otherwise EL3 15 12 3:0 AArch32 EL3 Exception level handling. All other values are reserved. EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state. 0b0000 EL3 is not implemented or can be executed in AArch64 state. 0b0001 EL3 can be executed in AArch32 state only. RO When EDPFR.EL3 == '0000' 15 12 15:12 Reserved, RAZ. Otherwise EL2 11 8 3:0 AArch32 EL2 Exception level handling. All other values are reserved. EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state. 0b0000 EL2 is not implemented or can be executed in AArch64 state. 0b0001 EL2 can be executed in AArch32 state only. RO When EDPFR.EL2 == '0000' 11 8 11:8 Reserved, RAZ. Otherwise PMSA 7 4 7:4 Indicates support for a 32-bit PMSA. In Armv8-A, the only permitted value is 0b0000. All other values are reserved. 0b0000 PMSA-32 not supported. 0b0100 PMSAv8-32 supported. RO VMSA 3 0 3:0 Indicates support for a VMSA in addition to a 32-bit PMSA. All other values are reserved. 0b0000 VMSA not supported. RO When EDAA32PFR.PMSA != '0000' VMSA 3 0 3:0 All other values are reserved. In Armv8-A, the only permitted value is 0b0000. 0b0000 VMSAv8-64 supported. 0b1111 Memory system architecture described by EDAA32PFR.MSA_frac. RO When EDAA32PFR.PMSA == '0000' 3 0 3:0 Reserved, RAZ. Otherwise 2026-03-26 20:27:25 2026-03_rel