EDACR External Debug Auxiliary Control Register When FEAT_DoPD is implemented, EDACR is in the Core power domain. Otherwise, it is IMPLEMENTATION DEFINED whether EDACR is implemented in the Core power domain or in the Debug power domain Implementation of this register is OPTIONAL. Debug 0x094 EDACR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() IMPDEF When SoftwareLockStatus(addrdesc) RO RW Allows implementations to support IMPLEMENTATION DEFINED controls. Debug If this register is implemented, EDDEVID.AuxRegs == 0b0001. If FEAT_DoPD is implemented, any mechanism to preserve control bits in EDACR over power down is optional and IMPLEMENTATION DEFINED. If FEAT_DoPD is not implemented and EDACR contains any control bits that must be preserved over power down, then these bits must be accessible by the external debug interface when the OS Lock is locked, OSLSR_EL1.OSLK == 1, and when the Core is powered off. Changing this register from its reset value causes IMPLEMENTATION DEFINED behavior, including possible deviation from the architecturally-defined behavior. EDACR is a 32-bit register. IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. The following resets apply: If the register is implemented in the Core power domain: On a Cold reset, this field resets to an architecturally UNKNOWN value. On an External debug reset, the value of this field is unchanged. On a Warm reset, the value of this field is unchanged. If the register is implemented in the External debug power domain: On a Cold reset, the value of this field is unchanged. On an External debug reset, this field resets to an architecturally UNKNOWN value. On a Warm reset, the value of this field is unchanged. 2026-03-26 20:27:25 2026-03_rel