<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>EDDEVID</reg_short_name>
        
        <reg_long_name>External Debug Device ID register 0</reg_long_name>

        <power_domain_text>When FEAT_DoPD is implemented, EDDEVID is in the Core power domain. Otherwise, EDDEVID is in the Debug power domain</power_domain_text>


      
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>Debug</reg_component>
    <reg_offset><hexnumber>0xFC8</hexnumber></reg_offset>
    <reg_instance>EDDEVID</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_DoPD is implemented and !IsCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides extra information for external debuggers about features of the debug implementation.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>Identification Registers</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>EDDEVID is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_28" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>28</field_lsb>
    <rel_range>31:28</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-27_24" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>AuxRegs</field_name>
    <field_msb>27</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>27:24</rel_range>
    <field_description order="before">
      <para>Indicates support for Auxiliary registers.</para>
    </field_description>
    <field_description order="after">
      <para>All other values are reserved.</para>
    </field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0b0000</field_value>
        <field_value_description>
          <para>None supported.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b0001</field_value>
        <field_value_description>
          <para>Support for External Debug Auxiliary Control Register, <register_link state="ext" id="ext-edacr.xml">EDACR</register_link>.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-23_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>23</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>23:8</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-7_4" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>DebugPower</field_name>
    <field_msb>7</field_msb>
    <field_lsb>4</field_lsb>
    <rel_range>7:4</rel_range>
    <field_description order="before">
      <para>Indicates support for the <xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> feature.</para>
    </field_description>
    <field_description order="after"><para><xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> implements the functionality added by the value <binarynumber>0b0001</binarynumber>.</para>
<para>All other values are reserved.</para></field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0b0000</field_value>
        <field_value_description>
          <para><xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> not implemented. Registers in the external debug interface register map are implemented in a mix of the Debug and Core power domains.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b0001</field_value>
        <field_value_description>
          <para><xref linkend="#FEAT_DoPD">FEAT_DoPD</xref> implemented. All registers in the external debug interface register map are implemented in the Core power domain.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-3_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PCSample</field_name>
    <field_msb>3</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>3:0</rel_range>
    <field_description order="before">
      <para>Indicates the level of PC Sample-based Profiling support using external debug registers.</para>
    </field_description>
    <field_description order="after"><para>All other values are reserved.</para>
<para>When <xref linkend="#FEAT_PCSRv8p2">FEAT_PCSRv8p2</xref> is implemented, the only permitted value is <binarynumber>0b0000</binarynumber>.</para>
<note><para><xref linkend="#FEAT_PCSRv8p2">FEAT_PCSRv8p2</xref> implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of <register_link id="pmu.pmdevid.xml" state="">PMDEVID</register_link>.PCSample.</para></note></field_description>
    <field_values impdef="True">
      <field_value_instance>
        <field_value>0b0000</field_value>
        <field_value_description>
          <para>PC Sample-based Profiling Extension is not implemented in the external debug registers space.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b0010</field_value>
        <field_value_description>
          <para>Only <register_link state="ext" id="ext-edpcsr.xml">EDPCSR</register_link> and <register_link state="ext" id="ext-edcidsr.xml">EDCIDSR</register_link> are implemented. This option is only permitted if EL3 and EL2 are not implemented.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b0011</field_value>
        <field_value_description>
          <para><register_link state="ext" id="ext-edpcsr.xml">EDPCSR</register_link>, <register_link state="ext" id="ext-edcidsr.xml">EDCIDSR</register_link>, and <register_link state="ext" id="ext-edvidsr.xml">EDVIDSR</register_link> are implemented.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_28" msb="31" lsb="28"/>
  <fieldat id="fieldset_0-27_24" msb="27" lsb="24"/>
  <fieldat id="fieldset_0-23_8" msb="23" lsb="8"/>
  <fieldat id="fieldset_0-7_4" msb="7" lsb="4"/>
  <fieldat id="fieldset_0-3_0" msb="3" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>