EDDEVID1 External Debug Device ID Register 1 When FEAT_DoPD is implemented, EDDEVID1 is in the Core power domain. Otherwise, EDDEVID1 is in the Debug power domain Debug 0xFC4 EDDEVID1 When FEAT_DoPD is implemented and !IsCorePowered() ERROR RO Provides extra information for external debuggers about features of the debug implementation. Identification Registers EDDEVID1 is a 32-bit register. 31 8 31:8 Reserved, RES0. HSR 7 4 7:4 Indicates support for the External Debug Halt Status Register, EDHSR. All other values are reserved. FEAT_EDHSR implements the functionality identified by the value 0b0001. FEAT_Debugv8p9 implements the functionality identified by the value 0b0010. When FEAT_Debugv8p2 is not implemented, the only permitted value is 0b0000. From Armv8.9, the values 0b0000 and 0b0001 are not permitted. 0b0000 EDHSR not implemented, and the PE follows behaviors consistent with all of the EDHSR fields having a zero value. 0b0001 EDHSR implemented. 0b0010 As 0b0001, but extends EDHSR to include the VNCR, CM, and WnR fields. RO PCSROffset 3 0 3:0 Indicates the offset applied to PC samples returned by reads of EDPCSR. When FEAT_PCSRv8p2 is implemented, the only permitted value is 0b0000. FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMDEVID.PCSample. 0b0000 EDPCSR not implemented. 0b0010 EDPCSR implemented, and samples have no offset applied and do not sample the instruction set state in AArch32 state. RO 2026-03-26 20:27:25 2026-03_rel