EDDFR External Debug Feature Register Debug 0xD28 EDDFR When IsCorePowered() and !DoubleLockStatus() RO When FEAT_DoPD is implemented and !IsCorePowered() ERROR IMPDEF Provides top-level information about the debug system. Debuggers must use EDDEVARCH to determine the Debug architecture version. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers EDDFR is a 64-bit register. 63 60 63:60 Reserved, UNKNOWN. ExtTrcBuff 59 56 59:56 Trace Buffer External Mode Extension. All other values are reserved. If FEAT_TRBE is not implemented, the only permitted value is 0b0000. FEAT_TRBE_EXT implements the functionality identified by the value 0b0001. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR0_EL1.ExtTrcBuff. 0b0000 Trace Buffer Extension not implemented or Trace Buffer External Mode not implemented. 0b0001 Trace Buffer Extension implemented and Trace Buffer External Mode implemented. RO 55 48 55:48 Reserved, UNKNOWN. TraceBuffer 47 44 3:0 Trace Buffer Extension. All other values are reserved. FEAT_TRBE implements the functionality identified by the value 0b0001. FEAT_TRBEv1p1 implements the functionality identified by the value 0b0010. In any Armv9 implementation, if FEAT_ETE is implemented, the value 0b0000 is not permitted. From Armv9.6, if FEAT_TRBE is implemented, the value 0b0001 is not permitted. 0b0000 Trace Buffer Extension not implemented. 0b0001 Trace Buffer Extension implemented. 0b0010 As 0b0001, and adds: If EL2 and FEAT_FGT are implemented, a fine-grained trap on the TSB CSYNC instruction. If EL2 is implemented, an EL2 control to override TRBLIMITR_EL1.nVM. The TRBE Profiling exception extension, FEAT_TRBE_EXC. RO When FEAT_TRBE_EXT is implemented 47 44 3:0 Reserved, UNKNOWN. Otherwise TraceFilt 43 40 43:40 Armv8.4 Self-hosted Trace Extension version. All other values are reserved. FEAT_TRF implements the functionality identified by the value 0b0001. From Armv8.4, if FEAT_ETMv4 is implemented, the value 0b0000 is not permitted. If FEAT_ETE is implemented, the value 0b0000 is not permitted. 0b0000 Armv8.4 Self-hosted Trace Extension not implemented. 0b0001 Armv8.4 Self-hosted Trace Extension implemented. RO 39 32 39:32 Reserved, UNKNOWN. CTX_CMPs 31 28 31:28 Number of context-aware breakpoints, minus 1. The value of this field is never greater than EDDFR.BRPs. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR0_EL1.CTX_CMPs. If FEAT_Debugv8p9 is implemented and 16 or more context-aware breakpoints are implemented, then this field reads as 0b1111 and EDDFR1.CTX_CMPs indicates the number of context-aware breakpoints. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints. 0b0000..0b1111 The number of context-aware breakpoints, minus 1. RO 27 24 27:24 Reserved, RES0. WRPs 23 20 23:20 Number of watchpoints, minus 1. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR0_EL1.WRPs. If FEAT_Debugv8p9 is implemented and 16 or more watchpoints are implemented, then this field reads as 0b1111 and EDDFR1.WRPs indicates the number of watchpoints. If AArch32 is supported at EL1, then the PE does not implement more than 16 watchpoints.The value 0b0000 is reserved. 0b0001..0b1111 The number of watchpoints, minus 1. RO PMSS 19 16 19:16 This field either has the same value as ID_AA64DFR0_EL1.PMSS or reads as zero. This field has an IMPLEMENTATION DEFINED value. RO BRPs 15 12 15:12 Number of breakpoints, minus 1. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR0_EL1.BRPs. If FEAT_Debugv8p9 is implemented and 16 or more breakpoints are implemented, then this field reads as 0b1111 and EDDFR1.BRPs indicates the number of breakpoints. If AArch32 is supported at EL1, then the PE does not implement more than 16 breakpoints.The value 0b0000 is reserved. 0b0001..0b1111 The number of breakpoints, minus 1. RO PMUVer 11 8 11:8 Performance Monitors Extension version. This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version' All other values are reserved. FEAT_PMUv3 implements the functionality identified by the value 0b0001. FEAT_PMUv3p1 implements the functionality identified by the value 0b0100. FEAT_PMUv3p4 implements the functionality identified by the value 0b0101. FEAT_PMUv3p5 implements the functionality identified by the value 0b0110. FEAT_PMUv3p7 implements the functionality identified by the value 0b0111. FEAT_PMUv3p8 implements the functionality identified by the value 0b1000. FEAT_PMUv3p9 implements the functionality identified by the value 0b1001. From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001 is not permitted. From Armv8.4, if FEAT_PMUv3 is implemented, the value 0b0100 is not permitted. From Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted. From Armv8.7, if FEAT_PMUv3 is implemented, the value 0b0110 is not permitted. From Armv8.8, if FEAT_PMUv3 is implemented, the value 0b0111 is not permitted. From Armv8.9, if FEAT_PMUv3 is implemented, the value 0b1000 is not permitted. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR0_EL1.PMUVer. 0b0000 Performance Monitors Extension not implemented. 0b0001 Performance Monitors Extension, PMUv3 implemented. 0b0100 PMUv3 for Armv8.1. As 0b0001, and adds support for: Extended 16-bit PMEVTYPER<n>_EL0.evtCount field. If EL2 is implemented, the MDCR_EL2.HPMD control. 0b0101 PMUv3 for Armv8.4. As 0b0100, and adds support for the PMMIR_EL1 register. 0b0110 PMUv3 for Armv8.5. As 0b0101, and adds support for: 64-bit event counters. If EL2 is implemented, the MDCR_EL2.HCCD control. If EL3 is implemented, the MDCR_EL3.SCCD control. 0b0111 PMUv3 for Armv8.7. As 0b0110, and adds support for: The PMCR_EL0.FZO and, if EL2 is implemented, MDCR_EL2.HPMFZO controls. If EL3 is implemented, the MDCR_EL3.{MPMX,MCCD} controls. 0b1000 PMUv3 for Armv8.8. As 0b0111, and: Extends the Common event number space to include 0x0040 to 0x00BF and 0x4040 to 0x40BF. Removes the CONSTRAINED UNPREDICTABLE behaviors if a reserved or unimplemented PMU event number is selected. 0b1001 PMUv3 for Armv8.9. As 0b1000, and: Updates the definitions of existing PMU events. Adds support for the PMUSERENR_EL0.UEN control and the PMUACR_EL1 register. Adds support for the EDECR.PME control. 0b1111 IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations. RO TraceVer 7 4 7:4 Trace support. Indicates whether System register interface to a trace unit is implemented. All other values are reserved. A value of 0b0000 only indicates that no System register interface to a trace unit is implemented. A trace unit might nevertheless be implemented without a System register interface. In an implementation that supports AArch64, this field returns the value of ID_AA64DFR0_EL1.TraceVer. 0b0000 Trace unit System registers not implemented. 0b0001 Trace unit System registers implemented. RO 3 0 3:0 Reserved, UNKNOWN. 2026-03-26 20:27:25 2026-03_rel