EDDFR2 External Debug Feature Register 2 Debug 0xD50 EDDFR2 When IsCorePowered(), !DoubleLockStatus(), and (!IsZero(EDDFR2()) or !OSLockStatus()) RO When FEAT_DoPD is implemented and !IsCorePowered() ERROR IMPDEF Provides top-level information about the debug system in AArch64. Identification Registers EDDFR2 is a 64-bit register. 63 28 63:28 Reserved, RES0. TRBE_EXC 27 24 27:24 This field either has the same value as ID_AA64DFR2_EL1.TRBE_EXC or reads as zero. This field has an IMPLEMENTATION DEFINED value. RO SPE_nVM 23 20 23:20 This field either has the same value as ID_AA64DFR2_EL1.SPE_nVM or reads as zero. This field has an IMPLEMENTATION DEFINED value. RO SPE_EXC 19 16 19:16 This field either has the same value as ID_AA64DFR2_EL1.SPE_EXC or reads as zero. This field has an IMPLEMENTATION DEFINED value. RO 15 8 15:8 Reserved, RES0. BWE 7 4 7:4 Breakpoints and watchpoint enhancements. All other values are reserved. FEAT_BWE implements the functionality identified by the value 0b0001. FEAT_BWE2 implements the functionality identified by the value 0b0010. When this field is 0b0000, ID_AA64DFR1_EL1.ABLE might indicate the presence of support for DBGBCR<n>_EL1.MASK and address mismatch breakpoints. From Armv9.5, the value 0b0001 is not permitted. In an implementation that supports AArch64, this field has the same value as ID_AA64DFR2_EL1.BWE. 0b0000 This field does not indicate whether DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented. 0b0001 DBGBCR<n>_EL1.MASK and address mismatch breakpoints are implemented. 0b0010 As 0b0001, and address mismatch watchpoints are implemented. RO STEP 3 0 3:0 This field either has the same value as ID_AA64DFR2_EL1.STEP or reads as zero. This field has an IMPLEMENTATION DEFINED value. RO 2026-03-26 20:27:25 2026-03_rel