EDECR External Debug Execution Control Register When FEAT_DoPD is implemented, EDECR is in the Core power domain. Otherwise, EDECR is in the Debug power domain Debug 0x024 EDECR When FEAT_DoPD is implemented and !IsCorePowered() ERROR When SoftwareLockStatus(addrdesc) RO RW Controls Halting debug events. Debug EDECR is a 32-bit register. 31 7 31:7 Reserved, RES0. TRBE 6 6 0 Trace Buffer External Debug Request Enable. This field is in the Core power domain. 0b0 Trace Buffer External Debug Request disabled. 0b1 Trace Buffer External Debug Request enabled. '0' When FEAT_Debugv8p9 is implemented and FEAT_TRBE_EXT is implemented 6 6 6 Reserved, RES0. Otherwise TRCE 5 5 0 ETE External Debug Request Enable. This field is in the Core power domain. 0b0 ETE External Debug Request disabled. 0b1 ETE External Debug Request enabled. '0' When FEAT_ETEv1p3 is implemented and FEAT_Debugv8p9 is implemented 5 5 5 Reserved, RES0. Otherwise PME 4 4 0 PMU Overflow External Debug Request Enable. This field is in the Core power domain. 0b0 PMU Overflow External Debug Request disabled. 0b1 PMU Overflow External Debug Request enabled. '0' When FEAT_Debugv8p9 is implemented and FEAT_PMUv3p9 is implemented 4 4 4 Reserved, RES0. Otherwise 3 3 3 Reserved, RES0. SS 2 2 2 Halting step enable. Possible values of this field are: If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state'. 0b0 Halting step debug event disabled. 0b1 Halting step debug event enabled. '0' '0' RCE 1 1 0 Reset Catch Enable. 0b0 Reset Catch debug event disabled. 0b1 Reset Catch debug event enabled. '0' When FEAT_DoPD is not implemented 1 1 0 Reserved, RES0. Otherwise OSUCE 0 0 0 OS Unlock Catch Enable. 0b0 OS Unlock Catch debug event disabled. 0b1 OS Unlock Catch debug event enabled. '0' When FEAT_DoPD is not implemented 0 0 0 Reserved, RES0. Otherwise 2026-03-26 20:27:25 2026-03_rel