EDITCTRL External Debug Integration mode Control register The power domain of EDITCTRL is IMPLEMENTATION DEFINED Implementation of this register is OPTIONAL. Debug 0xF00 EDITCTRL When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() IMPDEF When SoftwareLockStatus(addrdesc) RO RW Enables the external debug to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection. Debug EDITCTRL is a 32-bit register. 31 1 31:1 Reserved, RES0. IME 0 0 0 Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0b0 Normal operation. 0b1 Integration mode enabled. The following resets apply: Whichever power domain the register is implemented in, this field resets to 0. Otherwise, the value of this field is unchanged. 2026-03-26 20:27:25 2026-03_rel