EDITR External Debug Instruction Transfer Register EDITR is in the Core power domain Debug 0x084 EDITR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) WI WO Used in Debug state for passing instructions to the PE for execution. Debug EDITR is a 32-bit register. When FEAT_AA32 is implemented and UsingAArch32() in AArch32 state hw2 31 16 31:16 Second halfword of the T32 instruction to be executed on the PE. When EDITR contains a 16-bit T32 instruction, this field is ignored. For more information, see 'Behavior in Debug state'. The hw2 field is displayed on the left. This is not the usual convention for display of T32 instruction halfwords. hw1 15 0 15:0 First halfword of the T32 instruction to be executed on the PE. The hw1 field is displayed on the right. This is not the usual convention for display of T32 instruction halfwords. When FEAT_AA64 is implemented and !UsingAArch32() in AArch64 state A64_Instruction A64 instruction to be executed on the PE 31 0 31:0 A64 instruction to be executed on the PE. When FEAT_AA32 is implemented and UsingAArch32() When FEAT_AA64 is implemented and !UsingAArch32() If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any instruction issued through the ITR in Normal access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following: It must complete execution in Debug state before the PE executes the restart sequence. It must complete execution in Non-debug state before the PE executes the restart sequence. It must be abandoned. This means that the instruction does not execute. Any registers or memory accessed by the instruction are left in an UNKNOWN state. EDITR ignores writes if the PE is in Non-debug state. 2026-03-26 20:27:25 2026-03_rel