EDPCSR External Debug Program Counter Sample Register EDPCSR is in the Core power domain when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented Debug 0x0A0 EDPCSR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR RO Debug 0x0AC EDPCSR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR RO Holds a sampled instruction address value. Debug If FEAT_Debugv8p1 is implemented, the format of this register differs depending on the value of EDSCR.SC2. FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors registers space. EDPCSR is a 64-bit register. When FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == '0' FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == 0 EDPCSRhi PC Sample high word, EDPCSRhi 63 32 63:32 PC Sample high word, EDPCSRhi. If EDVIDSR.HV == 0, then this field is RAZ, otherwise bits [63:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}. AU EDPCSRlo PC Sample low word 31 0 31:0 PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value. EDPCSRlo reads as 0xFFFFFFFF when any of the following are true: The PE is in Debug state. PC Sample-based profiling is prohibited. If a branch instruction has retired since the PE left reset state, then the first read of EDPCSR[31:0] is permitted but not required to return 0xFFFFFFFF. EDPCSRlo reads as an UNKNOWN value when any of the following are true: The PE is in reset state. No branch instruction has retired since the PE left reset state, Debug state, or a state where PC Sample-based Profiling is prohibited. No branch instruction has retired since the last read of EDPCSR[31:0]. For the cases where a read of EDPCSR[31:0] returns 0xFFFFFFFF or an UNKNOWN value, the read has the side-effect of setting EDPCSRhi, EDCIDSR, and EDVIDSR to UNKNOWN values. Otherwise, a read of EDPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to EDPCSRhi, EDCIDSR, and EDVIDSR. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}. For a read of EDPCSR[31:0] from the memory-mapped interface, if EDLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the side-effect of the access does not occur and EDPCSRhi, EDCIDSR, and EDVIDSR are unchanged. AU When FEAT_Debugv8p1 is implemented and EDSCR.SC2 == '1' FEAT_Debugv8p1 is implemented and EDSCR.SC2 == 1 NS 63 63 63 Non-secure state sample. Indicates the Security state that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}. If EL3 is not implemented, this bit indicates the Effective value of SCR.NS. 0b0 Sample is from Secure state. 0b1 Sample is from Non-secure state. AU EL 62 61 62:61 Exception level status sample. Indicates the Exception level that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}. 0b00 Sample is from EL0. 0b01 Sample is from EL1. 0b10 Sample is from EL2. 0b11 Sample is from EL3. AU 60 56 60:56 Reserved, RES0. EDPCSRhi PC Sample high word, EDPCSRhi 55 32 55:32 PC Sample high word, EDPCSRhi. Bits [55:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}. AU EDPCSRlo PC Sample low word 31 0 31:0 PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value. EDPCSRlo reads as 0xFFFFFFFF when any of the following are true: The PE is in Debug state. PC Sample-based profiling is prohibited. If a branch instruction has retired since the PE left reset state, then the first read of EDPCSR[31:0] is permitted but not required to return 0xFFFFFFFF. EDPCSRlo reads as an UNKNOWN value when any of the following are true: The PE is in reset state. No branch instruction has retired since the PE left reset state, Debug state, or a state where PC Sample-based Profiling is prohibited. No branch instruction has retired since the last read of EDPCSR[31:0]. For the cases where a read of EDPCSR[31:0] returns 0xFFFFFFFF or an UNKNOWN value, the read has the side-effect of setting EDPCSRhi, EDCIDSR, and EDVIDSR to UNKNOWN values. Otherwise, a read of EDPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to EDPCSRhi, EDCIDSR, and EDVIDSR. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}. For a read of EDPCSR[31:0] from the memory-mapped interface, if EDLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the side-effect of the access does not occur and EDPCSRhi, EDCIDSR, and EDVIDSR are unchanged. AU When FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == '0' When FEAT_Debugv8p1 is implemented and EDSCR.SC2 == '1' IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' EDPCSR[63:32] and EDPCSR[31:0] are accessed at 32-bit memory mapped addresses that are not contiguous. 2026-03-26 20:27:25 2026-03_rel