EDPFR External Debug Processor Feature Register Debug 0xD20 EDPFR When IsCorePowered() and !DoubleLockStatus() RO When FEAT_DoPD is implemented and !IsCorePowered() ERROR IMPDEF Provides information about implemented PE features. For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'. Identification Registers EDPFR is a 64-bit register. 63 48 63:48 Reserved, UNKNOWN. AMU 47 44 47:44 Indicates support for Activity Monitors Extension. All other values are reserved. FEAT_AMUv1 implements the functionality identified by the value 0b0001. FEAT_AMUv1p1 implements the functionality identified by the value 0b0010. In Armv8.0, the only permitted value is 0b0000. In Armv8.4, the permitted values are 0b0000 and 0b0001. From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010. 0b0000 Activity Monitors Extension is not implemented. 0b0001 FEAT_AMUv1 is implemented. 0b0010 FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. RO 43 40 43:40 Reserved, UNKNOWN. SEL2 39 36 39:36 Secure EL2. FEAT_SEL2 implements the functionality identified by the value 0b0001 All other values are reserved. 0b0000 Secure EL2 is not implemented. 0b0001 Secure EL2 is implemented. RO SVE 35 32 35:32 Scalable Vector Extension. FEAT_SVE implements the functionality identified by the value 0b0001. All other values are reserved. 0b0000 SVE is not implemented. 0b0001 SVE is implemented. RO 31 28 31:28 Reserved, UNKNOWN. GIC 27 24 27:24 System register GIC interface support. All other values are reserved. In an implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.GIC. 0b0000 GIC CPU interface system registers not implemented. 0b0001 System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. 0b0011 System register interface to version 4.1 of the GIC CPU interface is supported. RO AdvSIMD 23 20 23:20 Advanced SIMD. All other values are reserved. This field must have the same value as the FP field. The permitted values are: 0b0000 in an implementation with Advanced SIMD support, that does not include the FEAT_FP16 extension. 0b0001 in an implementation with Advanced SIMD support, that includes the FEAT_FP16 extension. 0b1111 in an implementation without Advanced SIMD support. In an implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.AdvSIMD. 0b0000 Advanced SIMD is implemented, including support for the following SISD and SIMD operations: Integer byte, halfword, word and doubleword element operations. Single-precision and double-precision floating-point arithmetic. Conversions between single-precision and half-precision data types, and double-precision and half-precision data types. 0b0001 As for 0b0000, and also includes support for half-precision floating-point arithmetic. 0b1111 Advanced SIMD is not implemented. RO FP 19 16 19:16 Floating-point. All other values are reserved. This field must have the same value as the AdvSIMD field. The permitted values are: 0b0000 in an implementation with floating-point support, that does not include the FEAT_FP16 extension. 0b0001 in an implementation with floating-point support, that includes the FEAT_FP16 extension. 0b1111 in an implementation without floating-point support. In an implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.FP. 0b0000 Floating-point is implemented, and includes support for: Single-precision and double-precision floating-point types. Conversions between single-precision and half-precision data types, and double-precision and half-precision data types. 0b0001 As for 0b0000, and also includes support for half-precision floating-point arithmetic. 0b1111 Floating-point is not implemented. RO EL3 15 12 15:12 AArch64 EL3 Exception level handling. When the value of EDAA32PFR.EL3 is nonzero, this field must be 0b0000. All other values are reserved. In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL3. 0b0000 EL3 is not implemented or cannot be executed in AArch64 state. 0b0001 EL3 can be executed in AArch64 state only. 0b0010 EL3 can be executed in both Execution states. RO EL2 11 8 11:8 AArch64 EL2 Exception level handling. When the value of EDAA32PFR.EL2 is nonzero, this field must be 0b0000. All other values are reserved. In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL2. 0b0000 EL2 is not implemented or cannot be executed in AArch64 state. 0b0001 EL2 can be executed in AArch64 state only. 0b0010 EL2 can be executed in both Execution states. RO EL1 7 4 7:4 AArch64 EL1 Exception level handling. All other values are reserved. In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL1. 0b0000 EL1 cannot be executed in AArch64 state. EL1 can be executed in AArch32 state only. 0b0001 EL1 can be executed in AArch64 state only. 0b0010 EL1 can be executed in both Execution states. RO EL0 3 0 3:0 AArch64 EL0 Exception level handling. All other values are reserved. In an Armv8-A implementation that supports AArch64, this field returns the value of ID_AA64PFR0_EL1.EL0. 0b0000 EL0 cannot be executed in AArch64 state. EL0 can be executed in AArch32 state only. 0b0001 EL0 can be executed in AArch64 state only. 0b0010 EL0 can be executed in both Execution states. RO 2026-03-26 20:27:25 2026-03_rel