EDPRCR External Debug Power/Reset Control Register When FEAT_DoPD is implemented, EDPRCR is in the Core power domain. Otherwise, EDPRCR contains fields that are in the Core power domain and fields that are in the Debug power domain Debug 0x310 EDPRCR When FEAT_DoPD is implemented and !IsCorePowered() ERROR When SoftwareLockStatus(addrdesc) RO RW For RW fields see the field description for a description of the behavior of the field on a reset that applies to its power domain. However: Fields that are in the Core power domain are not affected by a warm reset and are not affected by an External debug reset. Fields that are in the Debug power domain reset to their defined reset values on an External debug reset, and are not affected by a Warm reset and are not affected by a Cold reset. DBGPRCR_EL1 Architectural AArch64 0 0 0 0 0 0 DBGPRCR Architectural AArch32 0 0 0 0 0 0 Controls the PE functionality related to powerup, reset, and powerdown. Debug EDPRCR is a 32-bit register. When FEAT_DoPD is implemented 31 2 31:2 Reserved, RES0. CWRR 1 1 0 RAZ/WI When FEAT_RME is implemented CWRR 1 1 0 Warm reset request. The extent of the reset is IMPLEMENTATION DEFINED, but must be one of: The request is ignored. Only this PE is Warm reset. This PE and other components of the system, possibly including other PEs, are Warm reset. Arm deprecates use of this bit, and recommends that implementations ignore the request. This field is in the Core power domain In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal. 0b0 No action. 0b1 Request Warm reset. '0' OSLockStatus() SoftwareLockStatus(addrdesc) RAZ/WI !ExternalSecureInvasiveDebugEnabled() FEAT_Secure is implemented RAZ/WI !ExternalInvasiveDebugEnabled() FEAT_Secure is not implemented RAZ/WI WO/RAZ Otherwise CORENPDRQ 0 0 0 Core no powerdown request. Requests emulation of powerdown. This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1. When this bit reads as UNKNOWN, the PE ignores writes to this bit. This field is in the Core power domain, and permitted accesses to this field map to the DBGPRCR.CORENPDRQ and DBGPRCR_EL1.CORENPDRQ fields. In an implementation that includes the recommended external debug interface, this bit drives the DBGNOPWRDWN signal. It is IMPLEMENTATION DEFINED whether this bit is reset to the Cold reset value on exit from an IMPLEMENTATION DEFINED software-visible retention state. For more information about retention states, see 'Core power domain power states'. Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted. 0b0 If the system responds to a powerdown request, it powers down Core power domain. 0b1 If the system responds to a powerdown request, it does not powerdown the Core power domain, but instead emulates a powerdown of that domain. On a Cold reset, if the powerup request is implemented and the powerup request has been asserted, this field is an IMPLEMENTATION DEFINED choice of 0 or 1. If the powerup request is not asserted, this field is set to 0. When OSLockStatus() UNKNOWN/WI When SoftwareLockStatus(addrdesc) RO RW 31 4 31:4 Reserved, RES0. COREPURQ 3 3 3 Core powerup request. Allows a debugger to request that the power controller power up the core, enabling access to the debug register in the Core power domain, and that the power controller emulates powerdown. This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1. In an implementation that includes the recommended external debug interface, this bit drives the DBGPWRUPREQ signal. This field is in the Debug power domain and can be read and written when the Core power domain is powered off. Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted. 0b0 Do not request power up of the Core power domain. 0b1 Request power up of the Core power domain, and emulation of powerdown. '0' When SoftwareLockStatus(addrdesc) RO RW 2 2 2 Reserved, RES0. CWRR 1 1 0 RAZ/WI When FEAT_RME is implemented CWRR 1 1 0 Warm reset request. The extent of the reset is IMPLEMENTATION DEFINED, but must be one of: The request is ignored. Only this PE is Warm reset. This PE and other components of the system, possibly including other PEs, are Warm reset. Arm deprecates use of this bit, and recommends that implementations ignore the request. This field is in the Core power domain In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal. 0b0 No action. 0b1 Request Warm reset. '0' !IsCorePowered() DoubleLockStatus() OSLockStatus() SoftwareLockStatus(addrdesc) RAZ/WI FEAT_Secure is implemented !ExternalSecureInvasiveDebugEnabled() RAZ/WI FEAT_Secure is not implemented !ExternalInvasiveDebugEnabled() RAZ/WI WO/RAZ Otherwise CORENPDRQ 0 0 0 Core no powerdown request. Requests emulation of powerdown. This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1. When this bit reads as UNKNOWN, the PE ignores writes to this bit. This field is in the Core power domain, and permitted accesses to this field map to the DBGPRCR.CORENPDRQ and DBGPRCR_EL1.CORENPDRQ fields. In an implementation that includes the recommended external debug interface, this bit drives the DBGNOPWRDWN signal. It is IMPLEMENTATION DEFINED whether this bit is reset to the value of EDPRCR.COREPURQ on exit from an IMPLEMENTATION DEFINED software-visible retention state. For more information about retention states, see 'Core power domain power states'. Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted. 0b0 If the system responds to a powerdown request, it powers down Core power domain. 0b1 If the system responds to a powerdown request, it does not powerdown the Core power domain, but instead emulates a powerdown of that domain. EDPRCR COREPURQ !IsCorePowered() DoubleLockStatus() OSLockStatus() UNKNOWN/WI When SoftwareLockStatus(addrdesc) RO RW When FEAT_DoPD is implemented On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information. 2026-03-26 20:27:25 2026-03_rel