EDPRSR
External Debug Processor Status Register
When FEAT_DoPD is implemented, EDPRSR is in the Core power domain. Otherwise, EDPRSR contains fields that are in the Core power domain and fields that are in the Debug power domain
Debug
0x314
EDPRSR
When FEAT_DoPD is implemented and !IsCorePowered()
ERROR
RO
Holds information about the reset and powerdown state of the PE.
Debug
If FEAT_DoPD is implemented, then all fields in this register are in the Core power domain.
EDPRSR is a 32-bit register.
31
17
31:17
Reserved, RES0.
EPMADE
16
16
0
External Performance Monitors Access Disable Extended status. Together with EDPRSR.EPMAD, reports whether access to Performance Monitor registers by an external debugger is prohibited by the MDCR_EL3.{EPMAD, EPMADE} controls.
For a description of the values derived by evaluating EDPRSR.EPMAD and EDPRSR.EPMADE together, see EDPRSR.EPMAD.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented and FEAT_PMUv3_EXT is implemented
16
16
16
Reserved, RES0.
Otherwise
ETADE
15
15
0
External Trace Access Disable Extended status. Together with EDPRSR.ETAD, reports whether access to trace unit registers by an external debugger is prohibited by the MDCR_EL3.{ETAD, ETADE} controls.
For a description of the values derived by evaluating EDPRSR.ETAD and EDPRSR.ETADE together, see EDPRSR.ETAD.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented, FEAT_TRC_EXT is implemented, and FEAT_TRBE is implemented
15
15
15
Reserved, RES0.
Otherwise
EDADE
14
14
0
External Debug Access Disable Extended status. Together with EDPRSR.EDAD, reports whether access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is prohibited by the MDCR_EL3.{EDAD, EDADE} controls.
For a description of the values derived by evaluating EDPRSR.EDAD and EDPRSR.EDADE together, see EDPRSR.EDAD.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented
14
14
14
Reserved, RES0.
Otherwise
STAD
13
13
0
Sticky ETAD error. Set to 1 when a Non-secure external debug interface access to an external trace register returns an error because AllowExternalTraceAccess() == FALSE for the access.
If IsCorePowered() == TRUE, the Core power domain is powered up, then, following a read of EDPRSR, then this bit clears to 0.
This field is in the Core power domain.
0b0
Since EDPRSR was last read, no external accesses to the trace unit registers have failed because AllowExternalTraceAccess() was FALSE for the access.
0b1
Since EDPRSR was last read, at least one external access to the trace unit registers has failed because AllowExternalTraceAccess() was FALSE for the access.
'0'
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
RC/WI
When FEAT_TRC_EXT is implemented and FEAT_TRBE is implemented
13
13
13
Reserved, RES0.
Otherwise
ETAD
12
12
0
External Trace Access Disable status. Together with EDPRSR.ETADE, reports whether access to trace unit registers by an external debugger is prohibited by the MDCR_EL3.{ETAD, ETADE} controls.
ETADEETADMeaning
0b00b0No accesses from an external debugger to trace unit registers are prohibited.
0b0
0b1
Realm and Non-secure accesses from an external debugger to trace unit registers are prohibited.
Other accesses from an external debugger to trace unit registers are not affected.
0b1
0b0
Secure and Non-secure accesses from an external debugger to trace unit registers are prohibited.
Other accesses from an external debugger to trace unit registers are not affected.
0b1
0b1
Secure, Non-secure, and Realm accesses from an external debugger to trace unit registers are prohibited.
Other accesses from an external debugger to trace unit registers are not affected.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented, FEAT_TRC_EXT is implemented, and FEAT_TRBE is implemented
ETAD
12
12
0
External Trace Access Disable status. Reports whether Non-secure access to trace unit registers by an external debugger is prohibited by the MDCR_EL3.ETAD control.
This field is in the Core power domain.
0b0
External Non-secure trace unit accesses not affected. AllowExternalTraceAccess() == TRUE for a Non-secure access.
0b1
External Non-secure trace unit accesses are prohibited. AllowExternalTraceAccess() == FALSE for a Non-secure access.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_TRC_EXT is implemented and FEAT_TRBE is implemented
12
12
12
Reserved, RES0.
Otherwise
SDR
11
11
11
Sticky Debug Restart. Set to 1 when the PE exits Debug state.
If a reset occurs when the PE is in Debug state, the PE exits Debug state. SDR is UNKNOWN on Warm reset, meaning a debugger must also use the SR bit to determine whether the PE has left Debug state.If the Core power domain is powered up, then following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
The PE has not restarted since EDPRSR was last read.
0b1
The PE has restarted since EDPRSR was last read.
AU
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
When SoftwareLockStatus(addrdesc)
RO
RC/WI
SPMAD
10
10
0
Sticky EPMAD error. Set to 1 if an external debug interface access to a Performance Monitors register returns an error because AllowExternalPMUAccess() == FALSE.
If the Core power domain is powered up, then following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
No Non-secure external debug interface accesses to the external Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.
0b1
At least one Non-secure external debug interface access to the external Performance Monitors register has failed and returned an error because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.
'0'
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
When SoftwareLockStatus(addrdesc)
RO
RC/WI
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3_EXT is implemented
SPMAD
10
10
0
Sticky EPMAD error.
If the Core power domain is powered up, then, following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented, and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
No external debug interface accesses to the Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.
0b1
At least one external debug interface access to the Performance Monitors registers has failed and returned an error because AllowExternalPMUAccess() == FALSE since EDPRSR was last read.
'0'
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
When OSLockStatus()
UNKNOWN/WI
When SoftwareLockStatus(addrdesc)
RO
RC/WI
When FEAT_PMUv3_EXT is implemented
10
10
10
Reserved, RES0.
Otherwise
EPMAD
9
9
0
External Performance Monitors Access Disable status. Together with EDPRSR.EPMADE, reports whether access to Performance Monitor registers by an external debugger is prohibited by the MDCR_EL3.{EPMAD, EPMADE} controls.
See MDCR_EL3.EPMAD for the list of affected external Performance Monitor registers.
EPMADEEPMADMeaning
0b00b0No accesses from an external debugger to affected Performance Monitor registers are prohibited.
0b0
0b1
Realm and Non-secure accesses from an external debugger to affected Performance Monitor registers are prohibited.
Other accesses from an external debugger to affected Performance Monitor registers are not affected.
0b1
0b0
Secure and Non-secure accesses from an external debugger to affected Performance Monitor registers are prohibited.
Other accesses from an external debugger to affected Performance Monitor registers are not affected.
0b1
0b1
Secure, Non-secure, and Realm accesses from an external debugger to affected Performance Monitor registers are prohibited.
Other accesses from an external debugger to affected Performance Monitor registers are not affected.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented and FEAT_PMUv3_EXT is implemented
EPMAD
9
9
0
External Performance Monitors Access Disable status. Reports whether Non-secure access to Performance Monitor registers by an external debugger is prohibited by the MDCR_EL3.EPMAD control.
See MDCR_EL3.EPMAD for the list of affected external Performance Monitor registers.
This field is in the Core power domain.
0b0
External Non-secure access to Performance Monitor registers not affected. AllowExternalPMUAccess() == TRUE for a Non-secure access.
0b1
External Non-secure access to affected Performance Monitor registers is prohibited. AllowExternalPMUAccess() == FALSE for a Non-secure access.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
RO
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3_EXT is implemented
EPMAD
9
9
0
External Performance Monitors Access Disable status. Reports whether access to Performance Monitor registers by an external debugger is prohibited by the MDCR_EL3.EPMAD control.
See MDCR_EL3.EPMAD for the list of affected external Performance Monitor registers.
This field is in the Core power domain.
0b0
External access to Performance Monitor registers not affected. AllowExternalPMUAccess() == TRUE.
0b1
External access to affected Performance Monitor registers is prohibited. AllowExternalPMUAccess() == FALSE.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
When OSLockStatus()
UNKNOWN/WI
RO
When FEAT_PMUv3_EXT is implemented
9
9
0
Reserved, UNKNOWN.
When FEAT_PMUv3 is implemented
9
9
9
Reserved, RES0.
Otherwise
SDAD
8
8
0
Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.
If the Core power domain is powered up, then, following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
No Non-secure external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.
0b1
At least one Non-secure external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE for the access since EDPRSR was last read.
'0'
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
RO
When FEAT_Debugv8p4 is implemented
SDAD
8
8
0
Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.
If the Core power domain is powered up, then, following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
No external debug interface accesses to the debug registers have failed because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.
0b1
At least one external debug interface access to the debug registers has failed and returned an error because AllowExternalDebugAccess() == FALSE since EDPRSR was last read.
'0'
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
OSLockStatus()
external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess(addrdesc) == FALSE
UNKNOWN/WI
RO
Otherwise
EDAD
7
7
0
External Debug Access Disable status. Together with EDPRSR.EDADE, reports whether access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is prohibited by the MDCR_EL3.{EDAD, EDADE} controls.
See MDCR_EL3.EDAD for the list of affected external debug registers.
EDADEEDADMeaning
0b00b0No accesses from an external debugger to affected debug registers are prohibited.
0b0
0b1
Realm and Non-secure accesses from an external debugger to affected debug registers are prohibited.
Other accesses from an external debugger to affected debug registers are not affected.
0b1
0b0
Secure and Non-secure accesses from an external debugger to affected debug registers are prohibited.
Other accesses from an external debugger to affected debug registers are not affected.
0b1
0b1
Secure, Non-secure, and Realm accesses from an external debugger to affected debug registers are prohibited.
Other accesses from an external debugger to affected debug registers are not affected.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
RO
When FEAT_RME is implemented
EDAD
7
7
0
External Debug Access Disable status. Reports whether Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is prohibited by the MDCR_EL3.EDAD control.
See MDCR_EL3.EDAD for the list of affected external debug registers.
This field is in the Core power domain.
0b0
External Non-secure access to debug registers not affected. AllowExternalDebugAccess() == TRUE for a Non-secure access.
0b1
External Non-secure access to affected debug registers is prohibited. AllowExternalDebugAccess() == FALSE for a Non-secure access.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
RO
When FEAT_Debugv8p4 is implemented
EDAD
7
7
0
External Debug Access Disable status. Reports whether access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger is prohibited by the MDCR_EL3.EDAD control.
See MDCR_EL3.EDAD for the list of affected external debug registers.
This field is in the Core power domain.
0b0
External access to debug registers not affected. AllowExternalDebugAccess() == TRUE.
0b1
External access to affected debug registers is prohibited. AllowExternalDebugAccess() == FALSE.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
OSLockStatus()
external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess(addrdesc) == FALSE
UNKNOWN/WI
RO
When FEAT_Debugv8p2 is implemented
EDAD
7
7
0
External Debug Access Disable status. Reports whether access to breakpoint registers, watchpoint registers, and optionally OSLAR_EL1 by an external debugger is prohibited by the MDCR_EL3.EDAD control.
See MDCR_EL3.EDAD for the list of affected external debug registers.
This field is in the Core power domain.
0b0
External access to debug registers not affected. AllowExternalDebugAccess() == TRUE.
0b1
External access to affected debug registers is prohibited. AllowExternalDebugAccess() == FALSE.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
RO
Otherwise
DLK
6
6
0
This field is RES0.
When FEAT_Debugv8p4 is implemented
DLK
6
6
0
Double Lock. From Armv8.2, use of this field is deprecated.
This field is in the Core power domain.
!IsCorePowered()
DoubleLockStatus()
UNKNOWN/WI
RAZ/WI
When FEAT_Debugv8p2 is implemented and FEAT_DoubleLock is implemented
DLK
6
6
0
Double Lock.
This field returns the result of the pseudocode function DoubleLockStatus().
If the Core power domain is powered up and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether:
EDPRSR.PU reads as 1, EDPRSR.DLK reads as 1, and EDPRSR.SPD is UNKNOWN.
EDPRSR.PU reads as 0, EDPRSR.DLK is UNKNOWN, and EDPRSR.SPD reads as 0.
This field is in the Core power domain.
0b0
DoubleLockStatus() returns FALSE.
0b1
DoubleLockStatus() returns TRUE and the Core power domain is powered up.
When !IsCorePowered()
UNKNOWN/WI
RO
When FEAT_DoubleLock is implemented
6
6
6
Reserved, RES0.
Otherwise
OSLK
5
5
5
OS Lock status bit.
A read of this bit returns the value of OSLSR_EL1.OSLK.
This field is in the Core power domain.
FEAT_DoPD is not implemented and !IsCorePowered()
EDPRSR.R == '1'
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
RO
HALTED
4
4
4
Halted status bit.
This field is in the Core power domain.
0b0
PE is in Non-debug state.
0b1
PE is in Debug state.
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
RO
SR
3
3
3
Sticky core Reset status bit.
If EDPRSR.PU reads as 1 and EDPRSR.R reads as 0, which means that the Core power domain is in a powerup state and that the non-debug logic of the PE is not in reset state, then following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
This field is in the Core power domain.
0b0
The non-debug logic of the PE is not in reset state and has not been reset since the last time EDPRSR was read.
0b1
The non-debug logic of the PE is in reset state or has been reset since the last time EDPRSR was read.
'1'
FEAT_DoPD is not implemented
!IsCorePowered()
UNKNOWN/WI
When DoubleLockStatus()
UNKNOWN/WI
When SoftwareLockStatus(addrdesc)
RO
RC/WI
R
2
2
2
PE Reset status bit.
If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information, see 'EDPRSR.{DLK, R} and reset state'.
This field is in the Core power domain.
0b0
The non-debug logic of the PE is not in reset state.
0b1
The non-debug logic of the PE is in reset state.
FEAT_DoPD is not implemented and !IsCorePowered()
DoubleLockStatus()
UNKNOWN/WI
RO
SPD
1
1
1
Sticky core Powerdown status bit.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, then:
If FEAT_Debugv8p2 is implemented, this bit reads as 0.
If FEAT_Debugv8p2 is not implemented, this bit might read as 0 or 1.
For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.
If the Core power domain is powered up, then, following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, this bit clears to 0.
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether this bit clears to 0 or is unchanged.
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.
When FEAT_DoPD is not implemented and the Core power domain is in either retention or powerdown state, the value of EDPRSR.SPD is IMPLEMENTATION DEFINED. For more information, see 'EDPRSR.SPD when the Core domain is in either retention or powerdown state'.
0b0
If EDPRSR.PU is 0, it is not known whether the state of the debug registers in the Core power domain is lost.
If EDPRSR.PU is 1, the state of the debug registers in the Core power domain has not been lost.
0b1
The state of the debug registers in the Core power domain has been lost.
'1'
FEAT_DoPD is not implemented
!IsCorePowered()
RAZ/WI
IsCorePowered()
DoubleLockStatus()
UNKNOWN/WI
RC/WI
PU
0
0
0
Core powerup status bit.
RAO/WI
When FEAT_DoPD is implemented
PU
0
0
0
Core Powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.
If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information, see 'EDPRSR.{DLK, R} and reset state'
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'
0b0
Either the Core power domain is in a low-power or powerdown state, or FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, meaning the debug registers in the Core power domain cannot be accessed.
0b1
The Core power domain is in a powerup state, and either FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, meaning the debug registers in the Core power domain can be accessed.
RO
When FEAT_Debugv8p2 is implemented
PU
0
0
0
Core Powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.
If FEAT_DoubleLock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state'
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} and the Core power domain'.
When the Core power domain is powered-up and DoubleLockStatus() == TRUE, then the value of EDPRSR.PU is IMPLEMENTATION DEFINED. See the description of the DLK bit for more information.
If FEAT_DoubleLock is implemented, the Core power domain is powered up, and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether this bit reads as 0 or 1.
0b0
Core power domain is in a low-power or powerdown state where the debug registers in the Core power domain cannot be accessed.
0b1
Core power domain is in a powerup state where the debug registers in the Core power domain can be accessed.
RO
Otherwise
On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.
If the Core power domain is powered up (EDPRSR.PU == 1), then following a read of EDPRSR:
If FEAT_DoubleLock is not implemented or DoubleLockStatus() == FALSE, then:
EDPRSR.{SDR, SPMAD, SDAD, SPD} are cleared to 0.
EDPRSR.SR is cleared to 0 if the non-debug logic of the PE is not in reset state (EDPRSR.R == 0).
If FEAT_DoubleLock is implemented and DoubleLockStatus() == TRUE, it is CONSTRAINED UNPREDICTABLE whether or not this clearing occurs.
If FEAT_DoPD is not implemented and the Core power domain is powered down (EDPRSR.PU == 0), then:
EDPRSR.{SDR, SPMAD, SDAD, SR} are all UNKNOWN, and are either reset or restored on being powered up.
EDPRSR.SPD is not cleared following a read of EDPRSR. See the SPD bit description for more information.
The clearing of bits is an indirect write to EDPRSR.
2026-03-26 20:27:25
2026-03_rel