EDRCR External Debug Reserve Control Register EDRCR is in the Core power domain Debug 0x090 EDRCR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) WI WO This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR. Debug EDRCR is a 32-bit register. 31 5 31:5 Reserved, RES0. CBRRQ 4 4 4 Allow imprecise entry to Debug state. The actions on writing to this bit are: Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1. This feature is optional. If this feature is not implemented, writes to this bit are ignored. 0b0 No action. 0b1 Allow imprecise entry to Debug state, for example by canceling pending bus accesses. CSPA 3 3 3 Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are: 0b0 No action. 0b1 Clear the EDSCR.PipeAdv bit to 0. CSE 2 2 2 Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: 0b0 No action. 0b1 Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the PE is in Debug state, the EDSCR.ITO bit, to 0. 1 0 1:0 Reserved, RES0. 2026-03-26 20:27:25 2026-03_rel